715 lines
18 KiB
C
715 lines
18 KiB
C
/* $NetBSD: vrgiu.c,v 1.34 2002/02/10 13:47:06 takemura Exp $ */
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/*-
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* Copyright (c) 1999-2001
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* Shin Takemura and PocketBSD Project. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the PocketBSD project
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* and its contributors.
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* 4. Neither the name of the project nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <sys/reboot.h>
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#include <mips/cpuregs.h>
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#include <machine/bus.h>
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#include <machine/config_hook.h>
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#include <machine/debug.h>
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#include <dev/hpc/hpciovar.h>
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#include "opt_vr41xx.h"
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#include <hpcmips/vr/vrcpudef.h>
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#include <hpcmips/vr/vripif.h>
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#include <hpcmips/vr/vripreg.h>
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#include <hpcmips/vr/vrgiureg.h>
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#include "locators.h"
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/*
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* constant and macro definitions
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*/
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#define VRGIUDEBUG
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#ifdef VRGIUDEBUG
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#define DEBUG_IO 1
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#define DEBUG_INTR 2
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#ifndef VRGIUDEBUG_CONF
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#define VRGIUDEBUG_CONF 0
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#endif /* VRGIUDEBUG_CONF */
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int vrgiu_debug = VRGIUDEBUG_CONF;
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#define DPRINTF(flag, arg) if (vrgiu_debug & flag) printf arg;
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#define DDUMP_IO(flag, sc) if (vrgiu_debug & flag) vrgiu_dump_io(sc);
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#define DDUMP_IOSETTING(flag, sc) \
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if (vrgiu_debug & flag) vrgiu_dump_iosetting(sc);
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#define VPRINTF(flag, arg) \
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if (bootverbose || vrgiu_debug & flag) printf arg;
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#define VDUMP_IO(flag, sc) \
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if (bootverbose || vrgiu_debug & flag) vrgiu_dump_io(sc);
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#define VDUMP_IOSETTING(flag, sc) \
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if (bootverbose || vrgiu_debug & flag) vrgiu_dump_iosetting(sc);
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#else
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#define DPRINTF(flag, arg)
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#define DDUMP_IO(flag, sc)
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#define DDUMP_IOSETTING(flag, sc)
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#define VPRINTF(flag, arg) if (bootverbose) printf arg;
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#define VDUMP_IO(flag, sc) if (bootverbose) vrgiu_dump_io(sc);
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#define VDUMP_IOSETTING(flag, sc) \
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if (bootverbose) vrgiu_dump_iosetting(sc);
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#endif
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#ifdef VRGIU_INTR_NOLED
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int vrgiu_intr_led = 0;
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#else /* VRGIU_INTR_NOLED */
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int vrgiu_intr_led = 1;
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#endif /* VRGIU_INTR_NOLED */
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#define MAX_GPIO_OUT 50 /* port 32:49 are output only port */
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#define MAX_GPIO_INOUT 32 /* input/output port(0:31) */
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#define LEGAL_INTR_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_INOUT)
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#define LEGAL_OUT_PORT(x) ((x) >= 0 && (x) < MAX_GPIO_OUT)
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/*
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* type declarations
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*/
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struct vrgiu_intr_entry {
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int ih_port;
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int (*ih_fun)(void *);
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void *ih_arg;
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TAILQ_ENTRY(vrgiu_intr_entry) ih_link;
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};
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struct vrgiu_softc {
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struct device sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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/* Interrupt */
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vrip_chipset_tag_t sc_vc;
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void *sc_ih;
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u_int32_t sc_intr_mask;
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u_int32_t sc_intr_mode[MAX_GPIO_INOUT];
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TAILQ_HEAD(, vrgiu_intr_entry) sc_intr_head[MAX_GPIO_INOUT];
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struct hpcio_chip sc_iochip;
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#ifndef SINGLE_VRIP_BASE
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int sc_useupdn_reg, sc_termupdn_reg;
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#endif /* SINGLE_VRIP_BASE */
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};
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#ifndef SINGLE_VRIP_BASE
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#define GIUUSEUPDN_REG_W (sc->sc_useupdn_reg)
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#define GIUTERMUPDN_REG_W (sc->sc_termupdn_reg)
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#endif /* SINGLE_VRIP_BASE */
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/*
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* prototypes
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*/
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int vrgiu_match(struct device*, struct cfdata*, void*);
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void vrgiu_attach(struct device*, struct device*, void*);
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int vrgiu_intr(void*);
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int vrgiu_print(void*, const char*);
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void vrgiu_callback(struct device*);
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void vrgiu_dump_regs(struct vrgiu_softc *);
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void vrgiu_dump_io(struct vrgiu_softc *);
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void vrgiu_diff_io(void);
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void vrgiu_dump_iosetting(struct vrgiu_softc *);
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void vrgiu_diff_iosetting(void);
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u_int32_t vrgiu_regread_4(struct vrgiu_softc *, bus_addr_t);
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u_int16_t vrgiu_regread(struct vrgiu_softc *, bus_addr_t);
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void vrgiu_regwrite_4(struct vrgiu_softc *, bus_addr_t, u_int32_t);
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void vrgiu_regwrite(struct vrgiu_softc *, bus_addr_t, u_int16_t);
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static int vrgiu_port_read(hpcio_chip_t, int);
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static void vrgiu_port_write(hpcio_chip_t, int, int);
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static void *vrgiu_intr_establish(hpcio_chip_t, int, int, int (*)(void *), void*);
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static void vrgiu_intr_disestablish(hpcio_chip_t, void*);
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static void vrgiu_intr_clear(hpcio_chip_t, void*);
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static void vrgiu_register_iochip(hpcio_chip_t, hpcio_chip_t);
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static void vrgiu_update(hpcio_chip_t);
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static void vrgiu_dump(hpcio_chip_t);
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static hpcio_chip_t vrgiu_getchip(void*, int);
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/*
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* variables
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*/
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static struct hpcio_chip vrgiu_iochip = {
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.hc_portread = vrgiu_port_read,
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.hc_portwrite = vrgiu_port_write,
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.hc_intr_establish = vrgiu_intr_establish,
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.hc_intr_disestablish = vrgiu_intr_disestablish,
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.hc_intr_clear = vrgiu_intr_clear,
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.hc_register_iochip = vrgiu_register_iochip,
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.hc_update = vrgiu_update,
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.hc_dump = vrgiu_dump,
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};
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struct cfattach vrgiu_ca = {
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sizeof(struct vrgiu_softc), vrgiu_match, vrgiu_attach
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};
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struct vrgiu_softc *this_giu;
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/*
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* function bodies
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*/
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int
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vrgiu_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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return (2); /* 1st attach group of vrip */
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}
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void
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vrgiu_attach(struct device *parent, struct device *self, void *aux)
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{
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struct vrip_attach_args *va = aux;
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struct vrgiu_softc *sc = (void*)self;
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struct hpcio_attach_args haa;
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int i;
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#ifndef SINGLE_VRIP_BASE
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if (va->va_addr == VR4102_GIU_ADDR) {
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sc->sc_useupdn_reg = VR4102_GIUUSEUPDN_REG_W;
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sc->sc_termupdn_reg = VR4102_GIUTERMUPDN_REG_W;
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} else
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if (va->va_addr == VR4122_GIU_ADDR) {
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sc->sc_useupdn_reg = VR4122_GIUUSEUPDN_REG_W;
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sc->sc_termupdn_reg = VR4122_GIUTERMUPDN_REG_W;
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} else {
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panic("%s: unknown base address 0x%lx\n",
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sc->sc_dev.dv_xname, va->va_addr);
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}
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#endif /* SINGLE_VRIP_BASE */
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this_giu = sc;
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sc->sc_vc = va->va_vc;
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sc->sc_iot = va->va_iot;
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bus_space_map(sc->sc_iot, va->va_addr, va->va_size,
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0 /* no cache */, &sc->sc_ioh);
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/*
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* Disable all interrupts.
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*/
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sc->sc_intr_mask = 0;
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printf("\n");
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#ifdef WINCE_DEFAULT_SETTING
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#warning WINCE_DEFAULT_SETTING
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#else
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VPRINTF(DEBUG_IO, (" "
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" 3 2 1\n"));
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VPRINTF(DEBUG_IO, (" "
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"10987654321098765432109876543210\n"));
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VPRINTF(DEBUG_IO, ("WIN setting: "));
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VDUMP_IOSETTING(DEBUG_IO, sc);
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VPRINTF(DEBUG_IO, ("\n"));
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vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask);
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#endif
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for (i = 0; i < MAX_GPIO_INOUT; i++)
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TAILQ_INIT(&sc->sc_intr_head[i]);
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if (!(sc->sc_ih = vrip_intr_establish(va->va_vc, va->va_unit, 0,
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IPL_BIO, vrgiu_intr, sc))) {
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printf("%s: can't establish interrupt\n", sc->sc_dev.dv_xname);
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return;
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}
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/*
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* fill hpcio_chip structure
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*/
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sc->sc_iochip = vrgiu_iochip; /* structure copy */
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sc->sc_iochip.hc_chipid = VRIP_IOCHIP_VRGIU;
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sc->sc_iochip.hc_name = sc->sc_dev.dv_xname;
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sc->sc_iochip.hc_sc = sc;
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/* Register functions to upper interface */
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vrip_register_gpio(va->va_vc, &sc->sc_iochip);
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/* Display port status (Input/Output) for debugging */
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VPRINTF(DEBUG_IO, ("I/O setting: "));
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VDUMP_IOSETTING(DEBUG_IO, sc);
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VPRINTF(DEBUG_IO, ("\n"));
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VPRINTF(DEBUG_IO, (" data:"));
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VDUMP_IO(DEBUG_IO, sc);
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/*
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* hpcio I/F
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*/
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haa.haa_busname = HPCIO_BUSNAME;
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haa.haa_sc = sc;
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haa.haa_getchip = vrgiu_getchip;
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haa.haa_iot = sc->sc_iot;
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while (config_found(self, &haa, vrgiu_print)) ;
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/*
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* GIU-ISA bridge
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*/
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#if 1 /* XXX Sometimes mounting root device failed. Why? XXX*/
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config_defer(self, vrgiu_callback);
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#else
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vrgiu_callback(self);
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#endif
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}
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void
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vrgiu_callback(struct device *self)
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{
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struct vrgiu_softc *sc = (void*)self;
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struct hpcio_attach_args haa;
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haa.haa_busname = "vrisab";
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haa.haa_sc = sc;
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haa.haa_getchip = vrgiu_getchip;
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haa.haa_iot = sc->sc_iot;
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config_found(self, &haa, vrgiu_print);
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}
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int
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vrgiu_print(void *aux, const char *pnp)
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{
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if (pnp)
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return (QUIET);
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return (UNCONF);
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}
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void
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vrgiu_dump_iosetting(struct vrgiu_softc *sc)
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{
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long iosel, inten, useupdn, termupdn, edge, hold, level;
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u_int32_t m;
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char syms[] = "iiiiiiiilhLHeeEEoooooooooooooooo"
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"DDDDDDDDDDDDDDDDUUUUUUUUUUUUUUUU";
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iosel= vrgiu_regread_4(sc, GIUIOSEL_REG);
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inten= vrgiu_regread_4(sc, GIUINTEN_REG);
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edge = vrgiu_regread_4(sc, GIUINTTYP_REG);
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hold = vrgiu_regread_4(sc, GIUINTHTSEL_REG);
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level = vrgiu_regread_4(sc, GIUINTALSEL_REG);
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if (GIUUSEUPDN_REG_W == GIU_NO_REG_W)
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useupdn = 0;
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else
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useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W);
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if (GIUTERMUPDN_REG_W == GIU_NO_REG_W)
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termupdn = 0;
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else
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termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W);
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for (m = 0x80000000; m; m >>=1)
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printf ("%c", syms[
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((useupdn&m) ? 32 : 0) +
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((iosel&m) ? 16 : 0) + ((termupdn&m) ? 16 : 0) +
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((inten&m) ? 8 : 0) +
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((edge&m) ? 4 : 0) +
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((hold&m) ? 2 : 0) +
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((level&m) ? 1 : 0)]);
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}
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void
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vrgiu_diff_iosetting()
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{
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struct vrgiu_softc *sc = this_giu;
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static long oiosel = 0, ointen = 0, ouseupdn = 0, otermupdn = 0;
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long iosel, inten, useupdn, termupdn;
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u_int32_t m;
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iosel= vrgiu_regread_4(sc, GIUIOSEL_REG);
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inten= vrgiu_regread_4(sc, GIUINTEN_REG);
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if (GIUUSEUPDN_REG_W == GIU_NO_REG_W)
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useupdn = 0;
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else
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useupdn = vrgiu_regread(sc, GIUUSEUPDN_REG_W);
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if (GIUTERMUPDN_REG_W == GIU_NO_REG_W)
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termupdn = 0;
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else
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termupdn = vrgiu_regread(sc, GIUTERMUPDN_REG_W);
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if (oiosel != iosel || ointen != inten ||
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ouseupdn != useupdn || otermupdn != termupdn) {
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for (m = 0x80000000; m; m >>=1)
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printf ("%c" , (useupdn&m) ?
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((termupdn&m) ? 'U' : 'D') :
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((iosel&m) ? 'o' : ((inten&m)?'I':'i')));
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}
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oiosel = iosel;
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ointen = inten;
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ouseupdn = useupdn;
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otermupdn = termupdn;
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}
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void
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vrgiu_dump_io(struct vrgiu_softc *sc)
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{
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dbg_bit_print(vrgiu_regread_4(sc, GIUPIOD_REG));
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dbg_bit_print(vrgiu_regread_4(sc, GIUPODAT_REG));
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}
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void
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vrgiu_diff_io()
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{
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struct vrgiu_softc *sc = this_giu;
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static u_int32_t opreg[2] = {0, 0};
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u_int32_t preg[2];
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preg[0] = vrgiu_regread_4(sc, GIUPIOD_REG);
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preg[1] = vrgiu_regread_4(sc, GIUPODAT_REG);
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if (opreg[0] != preg[0] || opreg[1] != preg[1]) {
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printf("giu data: ");
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dbg_bit_print(preg[0]);
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dbg_bit_print(preg[1]);
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}
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opreg[0] = preg[0];
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opreg[1] = preg[1];
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}
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void
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vrgiu_dump_regs(struct vrgiu_softc *sc)
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{
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if (sc == NULL) {
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panic("%s(%d): VRGIU device not initialized\n",
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__FILE__, __LINE__);
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}
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printf(" IOSEL: %08x\n", vrgiu_regread_4(sc, GIUIOSEL_REG));
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printf(" PIOD: %08x\n", vrgiu_regread_4(sc, GIUPIOD_REG));
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printf(" PODAT: %08x\n", vrgiu_regread_4(sc, GIUPODAT_REG));
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printf(" INTSTAT: %08x\n", vrgiu_regread_4(sc, GIUINTSTAT_REG));
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printf(" INTEN: %08x\n", vrgiu_regread_4(sc, GIUINTEN_REG));
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printf(" INTTYP: %08x\n", vrgiu_regread_4(sc, GIUINTTYP_REG));
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printf(" INTALSEL: %08x\n", vrgiu_regread_4(sc, GIUINTALSEL_REG));
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printf(" INTHTSEL: %08x\n", vrgiu_regread_4(sc, GIUINTHTSEL_REG));
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}
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/*
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* GIU regster access method.
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*/
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u_int32_t
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vrgiu_regread_4(struct vrgiu_softc *sc, bus_addr_t offs)
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{
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u_int16_t reg[2];
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bus_space_read_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2);
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return (reg[0] | (reg[1] << 16));
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}
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u_int16_t
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vrgiu_regread(struct vrgiu_softc *sc, bus_addr_t off)
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{
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return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, off));
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}
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void
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vrgiu_regwrite_4(struct vrgiu_softc *sc, bus_addr_t offs, u_int32_t data)
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{
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u_int16_t reg[2];
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reg[0] = data & 0xffff;
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reg[1] = (data>>16)&0xffff;
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bus_space_write_region_2 (sc->sc_iot, sc->sc_ioh, offs, reg, 2);
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}
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|
|
|
void
|
|
vrgiu_regwrite(struct vrgiu_softc *sc, bus_addr_t off, u_int16_t data)
|
|
{
|
|
|
|
bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, data);
|
|
}
|
|
|
|
/*
|
|
* PORT
|
|
*/
|
|
int
|
|
vrgiu_port_read(hpcio_chip_t hc, int port)
|
|
{
|
|
struct vrgiu_softc *sc = hc->hc_sc;
|
|
int on;
|
|
|
|
if (!LEGAL_OUT_PORT(port))
|
|
panic("vrgiu_port_read: illegal gpio port");
|
|
|
|
if (port < 32)
|
|
on = (vrgiu_regread_4(sc, GIUPIOD_REG) & (1 << port));
|
|
else
|
|
on = (vrgiu_regread_4(sc, GIUPODAT_REG) & (1 << (port - 32)));
|
|
|
|
return (on ? 1 : 0);
|
|
}
|
|
|
|
void
|
|
vrgiu_port_write(hpcio_chip_t hc, int port, int onoff)
|
|
{
|
|
struct vrgiu_softc *sc = hc->hc_sc;
|
|
u_int32_t reg[2];
|
|
int bank;
|
|
|
|
if (!LEGAL_OUT_PORT(port))
|
|
panic("vrgiu_port_write: illegal gpio port");
|
|
|
|
reg[0] = vrgiu_regread_4(sc, GIUPIOD_REG);
|
|
reg[1] = vrgiu_regread_4(sc, GIUPODAT_REG);
|
|
bank = port < 32 ? 0 : 1;
|
|
if (bank == 1)
|
|
port -= 32;
|
|
|
|
if (onoff)
|
|
reg[bank] |= (1<<port);
|
|
else
|
|
reg[bank] &= ~(1<<port);
|
|
vrgiu_regwrite_4(sc, GIUPIOD_REG, reg[0]);
|
|
vrgiu_regwrite_4(sc, GIUPODAT_REG, reg[1]);
|
|
}
|
|
|
|
static void
|
|
vrgiu_update(hpcio_chip_t hc)
|
|
{
|
|
}
|
|
|
|
static void
|
|
vrgiu_dump(hpcio_chip_t hc)
|
|
{
|
|
}
|
|
|
|
static hpcio_chip_t
|
|
vrgiu_getchip(void* scx, int chipid)
|
|
{
|
|
struct vrgiu_softc *sc = scx;
|
|
|
|
return (&sc->sc_iochip);
|
|
}
|
|
|
|
/*
|
|
* Interrupt staff
|
|
*/
|
|
void *
|
|
vrgiu_intr_establish(
|
|
hpcio_chip_t hc,
|
|
int port, /* GPIO pin # */
|
|
int mode, /* GIU trigger setting */
|
|
int (*ih_fun)(void *),
|
|
void *ih_arg)
|
|
{
|
|
struct vrgiu_softc *sc = hc->hc_sc;
|
|
int s;
|
|
u_int32_t reg, mask;
|
|
struct vrgiu_intr_entry *ih;
|
|
|
|
if (!LEGAL_INTR_PORT(port))
|
|
panic ("vrgiu_intr_establish: bogus interrupt line.");
|
|
if (sc->sc_intr_mode[port] && mode != sc->sc_intr_mode[port])
|
|
panic ("vrgiu_intr_establish: bogus interrupt type.");
|
|
else
|
|
sc->sc_intr_mode[port] = mode;
|
|
mask = (1 << port);
|
|
|
|
s = splhigh();
|
|
|
|
if (!(ih = malloc(sizeof(struct vrgiu_intr_entry), M_DEVBUF, M_NOWAIT)))
|
|
panic ("vrgiu_intr_establish: no memory.");
|
|
|
|
DPRINTF(DEBUG_INTR, ("%s: port %d ", sc->sc_dev.dv_xname, port));
|
|
ih->ih_port = port;
|
|
ih->ih_fun = ih_fun;
|
|
ih->ih_arg = ih_arg;
|
|
TAILQ_INSERT_TAIL(&sc->sc_intr_head[port], ih, ih_link);
|
|
#ifdef WINCE_DEFAULT_SETTING
|
|
#warning WINCE_DEFAULT_SETTING
|
|
#else
|
|
/*
|
|
* Setup registers
|
|
*/
|
|
/* Input mode */
|
|
reg = vrgiu_regread_4(sc, GIUIOSEL_REG);
|
|
reg &= ~mask;
|
|
vrgiu_regwrite_4(sc, GIUIOSEL_REG, reg);
|
|
|
|
/* interrupt type */
|
|
reg = vrgiu_regread_4(sc, GIUINTTYP_REG);
|
|
DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "edge" : "level"));
|
|
if (mode & HPCIO_INTR_EDGE) {
|
|
DPRINTF(DEBUG_INTR, ("edge]"));
|
|
reg |= mask; /* edge */
|
|
} else {
|
|
DPRINTF(DEBUG_INTR, ("level]"));
|
|
reg &= ~mask; /* level */
|
|
}
|
|
vrgiu_regwrite_4(sc, GIUINTTYP_REG, reg);
|
|
|
|
/* interrupt level */
|
|
if (!(mode & HPCIO_INTR_EDGE)) {
|
|
reg = vrgiu_regread_4(sc, GIUINTALSEL_REG);
|
|
DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "high" : "low"));
|
|
if (mode & HPCIO_INTR_HIGH) {
|
|
DPRINTF(DEBUG_INTR, ("high]"));
|
|
reg |= mask; /* high */
|
|
} else {
|
|
DPRINTF(DEBUG_INTR, ("low]"));
|
|
reg &= ~mask; /* low */
|
|
}
|
|
vrgiu_regwrite_4(sc, GIUINTALSEL_REG, reg);
|
|
}
|
|
/* hold or through */
|
|
reg = vrgiu_regread_4(sc, GIUINTHTSEL_REG);
|
|
DPRINTF(DEBUG_INTR, ("[%s->",reg & mask ? "hold" : "through"));
|
|
if (mode & HPCIO_INTR_HOLD) {
|
|
DPRINTF(DEBUG_INTR, ("hold]"));
|
|
reg |= mask; /* hold */
|
|
} else {
|
|
DPRINTF(DEBUG_INTR, ("through]"));
|
|
reg &= ~mask; /* through */
|
|
}
|
|
vrgiu_regwrite_4(sc, GIUINTHTSEL_REG, reg);
|
|
#endif
|
|
/*
|
|
* clear interrupt status
|
|
*/
|
|
reg = vrgiu_regread_4(sc, GIUINTSTAT_REG);
|
|
reg &= ~mask;
|
|
vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg);
|
|
/*
|
|
* enable interrupt
|
|
*/
|
|
#ifdef WINCE_DEFAULT_SETTING
|
|
#warning WINCE_DEFAULT_SETTING
|
|
#else
|
|
sc->sc_intr_mask |= mask;
|
|
vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask);
|
|
/* Unmask GIU level 2 mask register */
|
|
vrip_intr_setmask2(sc->sc_vc, sc->sc_ih, (1<<port), 1);
|
|
#endif
|
|
splx(s);
|
|
|
|
DPRINTF(DEBUG_INTR, ("\n"));
|
|
|
|
return (ih);
|
|
}
|
|
|
|
void
|
|
vrgiu_intr_disestablish(hpcio_chip_t hc, void *arg)
|
|
{
|
|
struct vrgiu_intr_entry *ihe = arg;
|
|
struct vrgiu_softc *sc = hc->hc_sc;
|
|
int port = ihe->ih_port;
|
|
struct vrgiu_intr_entry *ih;
|
|
int s;
|
|
|
|
s = splhigh();
|
|
TAILQ_FOREACH(ih, &sc->sc_intr_head[port], ih_link) {
|
|
if (ih == ihe) {
|
|
TAILQ_REMOVE(&sc->sc_intr_head[port], ih, ih_link);
|
|
free(ih, M_DEVBUF);
|
|
if (TAILQ_EMPTY(&sc->sc_intr_head[port])) {
|
|
/* Disable interrupt */
|
|
#ifdef WINCE_DEFAULT_SETTING
|
|
#warning WINCE_DEFAULT_SETTING
|
|
#else
|
|
sc->sc_intr_mask &= ~(1<<port);
|
|
vrgiu_regwrite_4(sc, GIUINTEN_REG, sc->sc_intr_mask);
|
|
#endif
|
|
}
|
|
splx(s);
|
|
return;
|
|
}
|
|
}
|
|
panic("vrgiu_intr_disetablish: no such a handle.");
|
|
/* NOTREACHED */
|
|
}
|
|
|
|
/* Clear interrupt */
|
|
void
|
|
vrgiu_intr_clear(hpcio_chip_t hc, void *arg)
|
|
{
|
|
struct vrgiu_softc *sc = hc->hc_sc;
|
|
struct vrgiu_intr_entry *ihe = arg;
|
|
u_int32_t reg;
|
|
|
|
reg = vrgiu_regread_4(sc, GIUINTSTAT_REG);
|
|
vrgiu_regwrite_4(sc, GIUINTSTAT_REG, reg & ~(1 << ihe->ih_port));
|
|
}
|
|
|
|
static void
|
|
vrgiu_register_iochip(hpcio_chip_t hc, hpcio_chip_t iochip)
|
|
{
|
|
struct vrgiu_softc *sc = hc->hc_sc;
|
|
|
|
vrip_register_gpio(sc->sc_vc, iochip);
|
|
}
|
|
|
|
/* interrupt handler */
|
|
int
|
|
vrgiu_intr(void *arg)
|
|
{
|
|
#ifdef DUMP_GIU_LEVEL2_INTR
|
|
#warning DUMP_GIU_LEVEL2_INTR
|
|
static u_int32_t oreg;
|
|
#endif
|
|
struct vrgiu_softc *sc = arg;
|
|
int i;
|
|
u_int32_t reg;
|
|
int ledvalue = CONFIG_HOOK_LED_FLASH;
|
|
|
|
/* Get Level 2 interrupt status */
|
|
vrip_intr_getstatus2 (sc->sc_vc, sc->sc_ih, ®);
|
|
#ifdef DUMP_GIU_LEVEL2_INTR
|
|
#warning DUMP_GIU_LEVEL2_INTR
|
|
{
|
|
u_int32_t uedge, dedge, j;
|
|
for (j = 0x80000000; j > 0; j >>=1)
|
|
printf ("%c" , reg&j ? '|' : '.');
|
|
uedge = (reg ^ oreg) & reg;
|
|
dedge = (reg ^ oreg) & ~reg;
|
|
if (uedge || dedge) {
|
|
for (j = 0; j < 32; j++) {
|
|
if (uedge & (1 << j))
|
|
printf ("+%d", j);
|
|
else if (dedge & (1 << j))
|
|
printf ("-%d", j);
|
|
}
|
|
}
|
|
oreg = reg;
|
|
printf ("\n");
|
|
}
|
|
#endif
|
|
/* Clear interrupt */
|
|
vrgiu_regwrite_4(sc, GIUINTSTAT_REG, vrgiu_regread_4(sc, GIUINTSTAT_REG));
|
|
|
|
/* Dispatch handler */
|
|
for (i = 0; i < MAX_GPIO_INOUT; i++) {
|
|
if (reg & (1 << i)) {
|
|
register struct vrgiu_intr_entry *ih;
|
|
TAILQ_FOREACH(ih, &sc->sc_intr_head[i], ih_link) {
|
|
ih->ih_fun(ih->ih_arg);
|
|
}
|
|
}
|
|
}
|
|
|
|
if (vrgiu_intr_led)
|
|
config_hook_call(CONFIG_HOOK_SET, CONFIG_HOOK_LED,
|
|
(void *)&ledvalue);
|
|
return (0);
|
|
}
|