85 lines
2.9 KiB
C
85 lines
2.9 KiB
C
/* $NetBSD: tegra_timerreg.h,v 1.2 2015/12/22 22:10:36 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM_TEGRA_TIMERREG_H
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#define _ARM_TEGRA_TIMERREG_H
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#define TMR1_PTV_REG 0x00
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#define TMR1_PCR_REG 0x04
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#define TMR2_PTV_REG 0x08
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#define TMR2_PCR_REG 0x0c
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#define TMRUS_CNTR_1US_REG 0x10
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#define TMRUS_USEC_CFG_REG 0x14
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#define TMRUS_CNTR_FREEZE_REG 0x18
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#define TMR3_PTV_REG 0x50
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#define TMR3_PCR_REG 0x54
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#define TMR4_PTV_REG 0x58
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#define TMR4_PCR_REG 0x5c
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#define TMR5_PTV_REG 0x60
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#define TMR5_PCR_REG 0x64
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#define TMR6_PTV_REG 0x68
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#define TMR6_PCR_REG 0x6c
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#define TMR7_PTV_REG 0x70
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#define TMR7_PCR_REG 0x74
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#define TMR8_PTV_REG 0x78
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#define TMR8_PCR_REG 0x7c
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#define TMR9_PTV_REG 0x80
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#define TMR9_PCR_REG 0x84
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#define TMR0_PTV_REG 0x88
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#define TMR0_PCR_REG 0x8c
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#define TMR_PTV_EN __BIT(31)
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#define TMR_PTV_PER __BIT(30)
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#define TMR_PTV_VAL __BITS(28,0)
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#define TMR_PCR_INTR_CLR __BIT(30)
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#define TMR_PCR_VAL __BITS(28,0)
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#define WDT0_CONFIG_REG 0x100
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#define WDT0_STATUS_REG 0x104
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#define WDT0_COMMAND_REG 0x108
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#define WDT0_UNLOCK_PATTERN_REG 0x10c
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#define WDT1_CONFIG_REG 0x100
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#define WDT1_STATUS_REG 0x104
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#define WDT1_COMMAND_REG 0x108
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#define WDT1_UNLOCK_PATTERN_REG 0x10c
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#define WDT2_CONFIG_REG 0x100
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#define WDT2_STATUS_REG 0x104
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#define WDT2_COMMAND_REG 0x108
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#define WDT2_UNLOCK_PATTERN_REG 0x10c
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#define WDT3_CONFIG_REG 0x100
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#define WDT3_STATUS_REG 0x104
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#define WDT3_COMMAND_REG 0x108
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#define WDT3_UNLOCK_PATTERN_REG 0x10c
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#define WDT4_CONFIG_REG 0x100
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#define WDT4_STATUS_REG 0x104
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#define WDT4_COMMAND_REG 0x108
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#define WDT4_UNLOCK_PATTERN_REG 0x10c
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#endif /* _ARM_TEGRA_TIMERREG_H */
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