0af3fdefa2
# envstat -d tegrasoctherm0
Current CritMax WarnMax WarnMin CritMin Unit
CPU0: 27.500 degC
CPU1: 27.500 degC
CPU2: 29.500 degC
CPU3: 29.000 degC
MEM0: 26.500 degC
MEM1: 27.000 degC
GPU: 27.000 degC
PLLX: 28.000 degC
167 lines
5.8 KiB
C
167 lines
5.8 KiB
C
/* $NetBSD: tegra_reg.h,v 1.20 2015/11/21 22:55:32 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _ARM_TEGRA_REG_H
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#define _ARM_TEGRA_REG_H
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#define CONSADDR_VA (CONSADDR - TEGRA_APB_BASE + TEGRA_APB_VBASE)
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#define TEGRA_EXTMEM_BASE 0x80000000
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#define TEGRA_PCIE_OFFSET 0x01000000
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#define TEGRA_PCIE_SIZE 0x3f000000
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#define TEGRA_PCIE_RPCONF_BASE 0x01000000
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#define TEGRA_PCIE_RPCONF_SIZE 0x00002000
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#define TEGRA_PCIE_PADS_BASE 0x01003000
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#define TEGRA_PCIE_PADS_SIZE 0x00000800
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#define TEGRA_PCIE_AFI_BASE 0x01003800
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#define TEGRA_PCIE_AFI_SIZE 0x00000800
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#define TEGRA_PCIE_A1_BASE 0x01000000
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#define TEGRA_PCIE_A1_SIZE 0x01000000
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#define TEGRA_PCIE_A2_BASE 0x02000000
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#define TEGRA_PCIE_A2_SIZE 0x0e000000
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#define TEGRA_PCIE_A3_BASE 0x10000000
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#define TEGRA_PCIE_A3_SIZE 0x30000000
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#define TEGRA_PCIE_CONF_BASE 0x02000000
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#define TEGRA_PCIE_CONF_SIZE 0x01000000
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#define TEGRA_PCIE_IO_BASE 0x01800000 /* comment in tegra_pcie.c */
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#define TEGRA_PCIE_IO_SIZE 0x00800000
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#define TEGRA_PCIE_MEM_BASE 0x03000000
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#define TEGRA_PCIE_MEM_SIZE 0x0d000000
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#define TEGRA_PCIE_EXTC_BASE 0x10000000
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#define TEGRA_PCIE_EXTC_SIZE 0x10000000
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#define TEGRA_PCIE_PMEM_BASE 0x20000000
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#define TEGRA_PCIE_PMEM_SIZE 0x20000000
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#define TEGRA_HOST1X_BASE 0x50000000
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#define TEGRA_HOST1X_SIZE 0x00034000
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#define TEGRA_GHOST_BASE 0x54000000
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#define TEGRA_GHOST_SIZE 0x01000000
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#define TEGRA_GPU_BASE 0x57000000
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#define TEGRA_GPU_SIZE 0x02000000
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#define TEGRA_PPSB_BASE 0x60000000
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#define TEGRA_PPSB_SIZE 0x01000000
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#define TEGRA_APB_BASE 0x70000000
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#define TEGRA_APB_SIZE 0x01000000
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#define TEGRA_AHB_A2_BASE 0x7c000000
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#define TEGRA_AHB_A2_SIZE 0x02000000
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#define TEGRA_PPSB_VBASE 0xfd000000
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#define TEGRA_APB_VBASE 0xfe000000
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#define TEGRA_REF_FREQ 12000000
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/* APB */
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#define TEGRA_MPIO_OFFSET 0x00000000
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#define TEGRA_MPIO_SIZE 0x4000
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#define TEGRA_UARTA_OFFSET 0x00006000
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#define TEGRA_UARTA_SIZE 0x40
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#define TEGRA_UARTB_OFFSET 0x00006040
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#define TEGRA_UARTB_SIZE 0x40
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#define TEGRA_UARTC_OFFSET 0x00006200
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#define TEGRA_UARTC_SIZE 0x100
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#define TEGRA_UARTD_OFFSET 0x00006300
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#define TEGRA_UARTD_SIZE 0x100
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#define TEGRA_I2C1_OFFSET 0x0000c000
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#define TEGRA_I2C1_SIZE 0x100
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#define TEGRA_I2C2_OFFSET 0x0000c400
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#define TEGRA_I2C2_SIZE 0x100
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#define TEGRA_I2C3_OFFSET 0x0000c500
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#define TEGRA_I2C3_SIZE 0x100
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#define TEGRA_I2C4_OFFSET 0x0000c700
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#define TEGRA_I2C4_SIZE 0x100
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#define TEGRA_I2C5_OFFSET 0x0000d000
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#define TEGRA_I2C5_SIZE 0x100
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#define TEGRA_I2C6_OFFSET 0x0000d100
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#define TEGRA_I2C6_SIZE 0x100
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#define TEGRA_RTC_OFFSET 0x0000e000
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#define TEGRA_RTC_SIZE 0x100
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#define TEGRA_KBC_OFFSET 0x0000e200
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#define TEGRA_KBC_SIZE 0x100
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#define TEGRA_PMC_OFFSET 0x0000e400
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#define TEGRA_PMC_SIZE 0x800
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#define TEGRA_FUSE_OFFSET 0x0000f800
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#define TEGRA_FUSE_SIZE 0x00000400
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#define TEGRA_CEC_OFFSET 0x00015000
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#define TEGRA_CEC_SIZE 0x1000
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#define TEGRA_MC_OFFSET 0x00019000
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#define TEGRA_MC_SIZE 0x1000
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#define TEGRA_SATA_OFFSET 0x00020000
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#define TEGRA_SATA_SIZE 0x10000
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#define TEGRA_HDA_OFFSET 0x00030000
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#define TEGRA_HDA_SIZE 0x10000
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#define TEGRA_XUSB_PADCTL_OFFSET 0x0009f000
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#define TEGRA_XUSB_PADCTL_SIZE 0x1000
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#define TEGRA_XUSB_HOST_OFFSET 0x00090000
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#define TEGRA_XUSB_HOST_SIZE 0xa000
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#define TEGRA_SDMMC1_OFFSET 0x000b0000
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#define TEGRA_SDMMC1_SIZE 0x200
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#define TEGRA_SDMMC2_OFFSET 0x000b0200
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#define TEGRA_SDMMC2_SIZE 0x200
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#define TEGRA_SDMMC3_OFFSET 0x000b0400
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#define TEGRA_SDMMC3_SIZE 0x200
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#define TEGRA_SDMMC4_OFFSET 0x000b0600
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#define TEGRA_SDMMC4_SIZE 0x200
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#define TEGRA_XUSB_DEV_OFFSET 0x000d0000
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#define TEGRA_XUSB_DEV_SIZE 0xa000
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#define TEGRA_SOC_THERM_OFFSET 0x000e2000
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#define TEGRA_SOC_THERM_SIZE 0x1000
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/* PPSB */
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#define TEGRA_TIMER_OFFSET 0x00005000
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#define TEGRA_TIMER_SIZE 0x400
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#define TEGRA_CAR_OFFSET 0x00006000
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#define TEGRA_CAR_SIZE 0x1000
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#define TEGRA_GPIO_OFFSET 0x0000d000
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#define TEGRA_GPIO_SIZE 0x00000800
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#define TEGRA_EVP_OFFSET 0x0000f000
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#define TEGRA_EVP_SIZE 0x1000
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/* AHB_A2 */
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#define TEGRA_USB1_OFFSET 0x01000000
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#define TEGRA_USB1_SIZE 0x1800
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#define TEGRA_USB2_OFFSET 0x01004000
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#define TEGRA_USB2_SIZE 0x1800
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#define TEGRA_USB3_OFFSET 0x01008000
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#define TEGRA_USB3_SIZE 0x1800
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/* Graphics Host (GHOST) */
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#define TEGRA_DISPLAYA_OFFSET 0x00200000
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#define TEGRA_DISPLAYA_SIZE 0x00040000
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#define TEGRA_DISPLAYB_OFFSET 0x00240000
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#define TEGRA_DISPLAYB_SIZE 0x00040000
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#define TEGRA_HDMI_OFFSET 0x00280000
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#define TEGRA_HDMI_SIZE 0x00040000
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#define TEGRA_SOR_OFFSET 0x00540000
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#define TEGRA_SOR_SIZE 0x00040000
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#define TEGRA_DPAUX_OFFSET 0x005c0000
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#define TEGRA_DPAUX_SIZE 0x00040000
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#endif /* _ARM_TEGRA_REG_H */
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