393 lines
14 KiB
C
393 lines
14 KiB
C
/* $NetBSD: bus_defs.h,v 1.3 2023/01/27 20:05:03 tsutsui Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#ifndef _ATARI_BUS_DEFS_H_
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#define _ATARI_BUS_DEFS_H_
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/*
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* Memory addresses (in bus space)
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*/
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typedef u_long bus_addr_t;
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typedef u_long bus_size_t;
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#define PRIxBUSADDR "lx"
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#define PRIxBUSSIZE "lx"
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#define PRIuBUSSIZE "lu"
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/*
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* I/O addresses (in bus space)
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*/
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typedef u_long bus_io_addr_t;
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typedef u_long bus_io_size_t;
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#define __BUS_SPACE_HAS_STREAM_METHODS
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/*
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* Access methods for bus resources and address space.
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*/
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typedef struct atari_bus_space *bus_space_tag_t;
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typedef u_long bus_space_handle_t;
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#define PRIxBSH "lx"
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#define BUS_SPACE_MAP_CACHEABLE 0x01
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#define BUS_SPACE_MAP_LINEAR 0x02
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#define BUS_SPACE_MAP_PREFETCHABLE 0x04
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/*
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* Structure containing functions and other feature-data that might differ
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* between the various bus spaces on the atari. Currently 'known' bus
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* spaces are: ISA, PCI, VME and 'mainbus'.
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*/
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struct atari_bus_space {
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u_long base;
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/* XXX Next 2 lines can be turned into an opaque cookie */
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int stride;
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int wo_1, wo_2, wo_4, wo_8;
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/* Autoconf detection stuff */
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int (*abs_p_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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int (*abs_p_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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int (*abs_p_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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int (*abs_p_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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/* read (single) */
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uint8_t (*abs_r_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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uint16_t (*abs_r_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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uint32_t (*abs_r_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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uint64_t (*abs_r_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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/* read (single) stream */
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uint8_t (*abs_rs_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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uint16_t (*abs_rs_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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uint32_t (*abs_rs_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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uint64_t (*abs_rs_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t);
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/* read multiple */
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void (*abs_rm_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint8_t *, bus_size_t);
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void (*abs_rm_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint16_t *, bus_size_t);
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void (*abs_rm_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint32_t *, bus_size_t);
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void (*abs_rm_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint64_t *, bus_size_t);
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/* read multiple stream */
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void (*abs_rms_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint8_t *, bus_size_t);
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void (*abs_rms_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint16_t *, bus_size_t);
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void (*abs_rms_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint32_t *, bus_size_t);
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void (*abs_rms_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint64_t *, bus_size_t);
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/* read region */
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void (*abs_rr_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint8_t *, bus_size_t);
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void (*abs_rr_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint16_t *, bus_size_t);
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void (*abs_rr_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint32_t *, bus_size_t);
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void (*abs_rr_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint64_t *, bus_size_t);
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/* read region stream */
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void (*abs_rrs_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint8_t *, bus_size_t);
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void (*abs_rrs_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint16_t *, bus_size_t);
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void (*abs_rrs_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint32_t *, bus_size_t);
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void (*abs_rrs_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint64_t *, bus_size_t);
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/* write (single) */
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void (*abs_w_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint8_t);
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void (*abs_w_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint16_t);
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void (*abs_w_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint32_t);
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void (*abs_w_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint64_t);
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/* write (single) stream */
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void (*abs_ws_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint8_t);
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void (*abs_ws_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint16_t);
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void (*abs_ws_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint32_t);
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void (*abs_ws_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint64_t);
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/* write multiple */
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void (*abs_wm_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint8_t *, bus_size_t);
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void (*abs_wm_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint16_t *, bus_size_t);
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void (*abs_wm_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint32_t *, bus_size_t);
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void (*abs_wm_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint64_t *, bus_size_t);
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/* write multiple stream */
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void (*abs_wms_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint8_t *, bus_size_t);
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void (*abs_wms_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint16_t *, bus_size_t);
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void (*abs_wms_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint32_t *, bus_size_t);
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void (*abs_wms_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint64_t *, bus_size_t);
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/* write region */
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void (*abs_wr_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint8_t *, bus_size_t);
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void (*abs_wr_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint16_t *, bus_size_t);
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void (*abs_wr_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint32_t *, bus_size_t);
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void (*abs_wr_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint64_t *, bus_size_t);
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/* write region stream */
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void (*abs_wrs_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint8_t *, bus_size_t);
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void (*abs_wrs_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint16_t *, bus_size_t);
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void (*abs_wrs_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint32_t *, bus_size_t);
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void (*abs_wrs_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, const uint64_t *, bus_size_t);
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/* set multiple */
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void (*abs_sm_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint8_t, bus_size_t);
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void (*abs_sm_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint16_t, bus_size_t);
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void (*abs_sm_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint32_t, bus_size_t);
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void (*abs_sm_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint64_t, bus_size_t);
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/* set region */
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void (*abs_sr_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint8_t, bus_size_t);
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void (*abs_sr_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint16_t, bus_size_t);
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void (*abs_sr_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint32_t, bus_size_t);
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void (*abs_sr_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, uint64_t, bus_size_t);
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#if 0 /* See comment on __abs_copy below */
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/* copy */
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void (*abs_c_1)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t,
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bus_size_t);
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void (*abs_c_2)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t,
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bus_size_t);
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void (*abs_c_4)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t,
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bus_size_t);
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void (*abs_c_8)(bus_space_tag_t, bus_space_handle_t,
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bus_size_t, bus_space_handle_t, bus_size_t,
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bus_size_t);
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#endif
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};
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#define BUS_SPACE_ALIGNED_POINTER(p, t) ALIGNED_POINTER(p, t)
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#define BUS_SPACE_BARRIER_READ 0x01 /* force read barrier */
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#define BUS_SPACE_BARRIER_WRITE 0x02 /* force write barrier */
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/*
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* Flags used in various bus DMA methods.
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*/
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#define BUS_DMA_WAITOK 0x000 /* safe to sleep (pseudo-flag) */
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#define BUS_DMA_NOWAIT 0x001 /* not safe to sleep */
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#define BUS_DMA_ALLOCNOW 0x002 /* perform resource allocation now */
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#define BUS_DMA_COHERENT 0x004 /* hint: map memory DMA coherent */
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#define BUS_DMA_STREAMING 0x008 /* hint: sequential, unidirectional */
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#define BUS_DMA_BUS1 0x010 /* placeholders for bus functions... */
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#define BUS_DMA_BUS2 0x020
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#define BUS_DMA_BUS3 0x040
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#define BUS_DMA_BUS4 0x080
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#define BUS_DMA_READ 0x100 /* mapping is device -> memory only */
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#define BUS_DMA_WRITE 0x200 /* mapping is memory -> device only */
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#define BUS_DMA_NOCACHE 0x400 /* hint: map non-cached memory */
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/* Forwards needed by prototypes below. */
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struct mbuf;
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struct uio;
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/*
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* Operations performed by bus_dmamap_sync().
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*/
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#define BUS_DMASYNC_PREREAD 0x01 /* pre-read synchronization */
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#define BUS_DMASYNC_POSTREAD 0x02 /* post-read synchronization */
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#define BUS_DMASYNC_PREWRITE 0x04 /* pre-write synchronization */
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#define BUS_DMASYNC_POSTWRITE 0x08 /* post-write synchronization */
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typedef struct atari_bus_dma_tag *bus_dma_tag_t;
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typedef struct atari_bus_dmamap *bus_dmamap_t;
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#define BUS_DMA_TAG_VALID(t) ((t) != (bus_dma_tag_t)0)
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/*
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* bus_dma_segment_t
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*
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* Describes a single contiguous DMA transaction. Values
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* are suitable for programming into DMA registers.
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*/
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struct atari_bus_dma_segment {
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bus_addr_t ds_addr; /* DMA address */
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bus_size_t ds_len; /* length of transfer */
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};
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typedef struct atari_bus_dma_segment bus_dma_segment_t;
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/*
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* bus_dma_tag_t
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*
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* A machine-dependent opaque type describing the implementation of
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* DMA for a given bus.
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*/
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struct atari_bus_dma_tag {
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/*
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* The `bounce threshold' is checked while we are loading
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* the DMA map. If the physical address of the segment
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* exceeds the threshold, an error will be returned. The
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* caller can then take whatever action is necessary to
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* bounce the transfer. If this value is 0, it will be
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* ignored.
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*/
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bus_addr_t _bounce_thresh;
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/*
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* The next value can be used to compensate for a constant
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* displacement between the address space view of the CPU
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* and the devices on the bus.
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*/
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int32_t _displacement;
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/*
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* DMA mapping methods.
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*/
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int (*_dmamap_create)(bus_dma_tag_t, bus_size_t, int,
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bus_size_t, bus_size_t, int, bus_dmamap_t *);
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void (*_dmamap_destroy)(bus_dma_tag_t, bus_dmamap_t);
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int (*_dmamap_load)(bus_dma_tag_t, bus_dmamap_t, void *,
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bus_size_t, struct proc *, int);
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int (*_dmamap_load_mbuf)(bus_dma_tag_t, bus_dmamap_t,
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struct mbuf *, int);
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int (*_dmamap_load_uio)(bus_dma_tag_t, bus_dmamap_t,
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struct uio *, int);
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int (*_dmamap_load_raw)(bus_dma_tag_t, bus_dmamap_t,
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bus_dma_segment_t *, int, bus_size_t, int);
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void (*_dmamap_unload)(bus_dma_tag_t, bus_dmamap_t);
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void (*_dmamap_sync)(bus_dma_tag_t, bus_dmamap_t,
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bus_addr_t, bus_size_t, int);
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};
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/*
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* bus_dmamap_t
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*
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* Describes a DMA mapping.
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*/
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struct atari_bus_dmamap {
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/*
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* PRIVATE MEMBERS: not for use my machine-independent code.
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*/
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bus_size_t _dm_size; /* largest DMA transfer mappable */
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int _dm_segcnt; /* number of segs this map can map */
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bus_size_t _dm_maxmaxsegsz; /* fixed largest possible segment */
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bus_size_t _dm_boundary; /* don't cross this */
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bus_addr_t _dm_bounce_thresh; /* bounce threshold; see tag */
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int _dm_flags; /* misc. flags */
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void *_dm_cookie; /* cookie for bus-specific funcs */
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/*
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* PUBLIC MEMBERS: these are used by machine-independent code.
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*/
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bus_size_t dm_maxsegsz; /* largest possible segment */
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bus_size_t dm_mapsize; /* size of the mapping */
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int dm_nsegs; /* # valid segments in mapping */
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bus_dma_segment_t dm_segs[1]; /* segments; variable length */
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};
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#endif /* _ATARI_BUS_DEFS_H_ */
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