450 lines
11 KiB
C
450 lines
11 KiB
C
/* $NetBSD: flsc.c,v 1.15 1997/08/27 11:23:08 bouyer Exp $ */
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/*
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* Copyright (c) 1995 Daniel Widenfalk
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* Copyright (c) 1994 Christian E. Hopps
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* Copyright (c) 1982, 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)dma.c
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <vm/vm.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_page.h>
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#include <machine/pmap.h>
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#include <amiga/amiga/custom.h>
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#include <amiga/amiga/cc.h>
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#include <amiga/amiga/device.h>
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#include <amiga/amiga/isr.h>
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#include <amiga/dev/sfasreg.h>
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#include <amiga/dev/sfasvar.h>
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#include <amiga/dev/zbusvar.h>
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#include <amiga/dev/flscreg.h>
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#include <amiga/dev/flscvar.h>
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void flscattach __P((struct device *, struct device *, void *));
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int flscmatch __P((struct device *, struct cfdata *, void *));
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struct scsipi_adapter flsc_scsiswitch = {
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sfas_scsicmd,
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sfas_minphys,
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0, /* no lun support */
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0, /* no lun support */
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};
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struct scsipi_device flsc_scsidev = {
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NULL, /* use default error handler */
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NULL, /* do not have a start functio */
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NULL, /* have no async handler */
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NULL, /* Use default done routine */
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};
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struct cfattach flsc_ca = {
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sizeof(struct flsc_softc), flscmatch, flscattach
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};
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struct cfdriver flsc_cd = {
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NULL, "flsc", DV_DULL, NULL, 0
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};
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int flsc_intr __P((void *));
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void flsc_set_dma_adr __P((struct sfas_softc *sc, vm_offset_t ptr));
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void flsc_set_dma_tc __P((struct sfas_softc *sc, unsigned int len));
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void flsc_set_dma_mode __P((struct sfas_softc *sc, int mode));
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int flsc_setup_dma __P((struct sfas_softc *sc, vm_offset_t ptr, int len,
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int mode));
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int flsc_build_dma_chain __P((struct sfas_softc *sc,
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struct sfas_dma_chain *chain, void *p, int l));
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int flsc_need_bump __P((struct sfas_softc *sc, vm_offset_t ptr, int len));
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void flsc_led __P((struct sfas_softc *sc, int mode));
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/*
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* if we are an Advanced Systems & Software FastlaneZ3
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*/
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int
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flscmatch(pdp, cfp, auxp)
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struct device *pdp;
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struct cfdata *cfp;
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void *auxp;
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{
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struct zbus_args *zap;
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if (!is_a4000() && !is_a3000())
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return(0);
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zap = auxp;
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if (zap->manid == 0x2140 && zap->prodid == 11
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&& iszthreepa(zap->pa))
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return(1);
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return(0);
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}
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void
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flscattach(pdp, dp, auxp)
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struct device *pdp;
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struct device *dp;
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void *auxp;
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{
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struct flsc_softc *sc;
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struct zbus_args *zap;
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flsc_regmap_p rp;
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vu_char *fas;
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zap = auxp;
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fas = &((vu_char *)zap->va)[0x1000001];
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sc = (struct flsc_softc *)dp;
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rp = &sc->sc_regmap;
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rp->FAS216.sfas_tc_low = &fas[0x00];
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rp->FAS216.sfas_tc_mid = &fas[0x04];
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rp->FAS216.sfas_fifo = &fas[0x08];
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rp->FAS216.sfas_command = &fas[0x0C];
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rp->FAS216.sfas_dest_id = &fas[0x10];
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rp->FAS216.sfas_timeout = &fas[0x14];
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rp->FAS216.sfas_syncper = &fas[0x18];
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rp->FAS216.sfas_syncoff = &fas[0x1C];
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rp->FAS216.sfas_config1 = &fas[0x20];
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rp->FAS216.sfas_clkconv = &fas[0x24];
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rp->FAS216.sfas_test = &fas[0x28];
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rp->FAS216.sfas_config2 = &fas[0x2C];
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rp->FAS216.sfas_config3 = &fas[0x30];
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rp->FAS216.sfas_tc_high = &fas[0x38];
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rp->FAS216.sfas_fifo_bot = &fas[0x3C];
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rp->hardbits = &fas[0x40];
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rp->clear = &fas[0x80];
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rp->dmabase = zap->va;
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sc->sc_softc.sc_fas = (sfas_regmap_p)rp;
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sc->sc_softc.sc_spec = &sc->sc_specific;
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sc->sc_softc.sc_led = flsc_led;
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sc->sc_softc.sc_setup_dma = flsc_setup_dma;
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sc->sc_softc.sc_build_dma_chain = flsc_build_dma_chain;
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sc->sc_softc.sc_need_bump = flsc_need_bump;
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sc->sc_softc.sc_clock_freq = 40; /* FastlaneZ3 runs at 40MHz */
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sc->sc_softc.sc_timeout = 250; /* Set default timeout to 250ms */
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sc->sc_softc.sc_config_flags = 0; /* No config flags yet */
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sc->sc_softc.sc_host_id = 7; /* Should check the jumpers */
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sc->sc_specific.portbits = 0xA0 | FLSC_PB_EDI | FLSC_PB_ESI;
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sc->sc_specific.hardbits = *rp->hardbits;
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sc->sc_softc.sc_bump_sz = NBPG;
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sc->sc_softc.sc_bump_pa = 0x0;
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sfasinitialize((struct sfas_softc *)sc);
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sc->sc_softc.sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE;
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sc->sc_softc.sc_link.adapter_softc = sc;
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sc->sc_softc.sc_link.scsipi_scsi.adapter_target = sc->sc_softc.sc_host_id;
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sc->sc_softc.sc_link.adapter = &flsc_scsiswitch;
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sc->sc_softc.sc_link.device = &flsc_scsidev;
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sc->sc_softc.sc_link.openings = 1;
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sc->sc_softc.sc_link.scsipi_scsi.max_target = 7;
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sc->sc_softc.sc_link.type = BUS_SCSI;
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sc->sc_softc.sc_isr.isr_intr = flsc_intr;
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sc->sc_softc.sc_isr.isr_arg = &sc->sc_softc;
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sc->sc_softc.sc_isr.isr_ipl = 2;
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add_isr(&sc->sc_softc.sc_isr);
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/* We don't want interrupt until we're initialized! */
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*rp->hardbits = sc->sc_specific.portbits;
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printf("\n");
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/* attach all scsi units on us */
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config_found(dp, &sc->sc_softc.sc_link, scsiprint);
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}
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int
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flsc_intr(arg)
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void *arg;
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{
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struct sfas_softc *dev = arg;
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flsc_regmap_p rp;
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struct flsc_specific *flspec;
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int quickints;
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u_char hb;
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flspec = dev->sc_spec;
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rp = (flsc_regmap_p)dev->sc_fas;
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hb = *rp->hardbits;
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if (hb & FLSC_HB_IACT)
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return(0);
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flspec->hardbits = hb;
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if ((hb & FLSC_HB_CREQ) &&
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!(hb & FLSC_HB_MINT) &&
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(*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING)) {
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quickints = 16;
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do {
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dev->sc_status = *rp->FAS216.sfas_status;
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dev->sc_interrupt = *rp->FAS216.sfas_interrupt;
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if (dev->sc_interrupt & SFAS_INT_RESELECTED) {
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dev->sc_resel[0] = *rp->FAS216.sfas_fifo;
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dev->sc_resel[1] = *rp->FAS216.sfas_fifo;
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}
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sfasintr(dev);
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} while((*rp->FAS216.sfas_status & SFAS_STAT_INTERRUPT_PENDING)
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&& --quickints);
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}
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/* Reset fastlane interrupt bits */
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*rp->hardbits = flspec->portbits & ~FLSC_PB_INT_BITS;
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*rp->hardbits = flspec->portbits;
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return(1);
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}
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/* Load transfer adress into dma register */
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void
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flsc_set_dma_adr(sc, ptr)
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struct sfas_softc *sc;
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vm_offset_t ptr;
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{
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flsc_regmap_p rp;
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unsigned int *p;
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unsigned int d;
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rp = (flsc_regmap_p)sc->sc_fas;
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d = (unsigned int)ptr;
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p = (unsigned int *)((d & 0xFFFFFF) + (int)rp->dmabase);
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*rp->clear=0;
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*p = d;
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}
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/* Set DMA transfer counter */
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void
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flsc_set_dma_tc(sc, len)
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struct sfas_softc *sc;
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unsigned int len;
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{
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*sc->sc_fas->sfas_tc_low = len; len >>= 8;
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*sc->sc_fas->sfas_tc_mid = len; len >>= 8;
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*sc->sc_fas->sfas_tc_high = len;
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}
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/* Set DMA mode */
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void
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flsc_set_dma_mode(sc, mode)
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struct sfas_softc *sc;
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int mode;
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{
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struct flsc_specific *spec;
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spec = sc->sc_spec;
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spec->portbits = (spec->portbits & ~FLSC_PB_DMA_BITS) | mode;
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*((flsc_regmap_p)sc->sc_fas)->hardbits = spec->portbits;
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}
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/* Initialize DMA for transfer */
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int
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flsc_setup_dma(sc, ptr, len, mode)
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struct sfas_softc *sc;
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vm_offset_t ptr;
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int len;
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int mode;
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{
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int retval;
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retval = 0;
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switch(mode) {
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case SFAS_DMA_READ:
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case SFAS_DMA_WRITE:
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flsc_set_dma_adr(sc, ptr);
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if (mode == SFAS_DMA_READ)
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flsc_set_dma_mode(sc,FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_READ);
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else
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flsc_set_dma_mode(sc,FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_WRITE);
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flsc_set_dma_tc(sc, len);
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break;
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case SFAS_DMA_CLEAR:
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default:
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flsc_set_dma_mode(sc, FLSC_PB_DISABLE_DMA);
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flsc_set_dma_adr(sc, 0);
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retval = (*sc->sc_fas->sfas_tc_high << 16) |
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(*sc->sc_fas->sfas_tc_mid << 8) |
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*sc->sc_fas->sfas_tc_low;
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flsc_set_dma_tc(sc, 0);
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break;
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}
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return(retval);
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}
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/* Check if address and len is ok for DMA transfer */
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int
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flsc_need_bump(sc, ptr, len)
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struct sfas_softc *sc;
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vm_offset_t ptr;
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int len;
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{
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int p;
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if (((int)ptr & 0x03) || (len & 0x03)) {
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if (len < 256)
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p = len;
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else
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p = 256;
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} else
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p = 0;
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return(p);
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}
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/* Interrupt driven routines */
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int
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flsc_build_dma_chain(sc, chain, p, l)
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struct sfas_softc *sc;
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struct sfas_dma_chain *chain;
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void *p;
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int l;
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{
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vm_offset_t pa, lastpa;
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char *ptr;
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int len, prelen, max_t, n;
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if (l == 0)
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return(0);
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#define set_link(n, p, l, f)\
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do { chain[n].ptr = (p); chain[n].len = (l); chain[n++].flg = (f); } while(0)
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n = 0;
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if (l < 512)
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set_link(n, (vm_offset_t)p, l, SFAS_CHAIN_BUMP);
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else if ((p >= (void *)0xFF000000)
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#if defined(M68040) || defined(M68060)
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&& ((mmutype == MMU_68040) && (p >= (void *)0xFFFC0000))
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#endif
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) {
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while(l != 0) {
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len = ((l > sc->sc_bump_sz) ? sc->sc_bump_sz : l);
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set_link(n, (vm_offset_t)p, len, SFAS_CHAIN_BUMP);
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p += len;
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l -= len;
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}
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} else {
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ptr = p;
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len = l;
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pa = kvtop(ptr);
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prelen = ((int)ptr & 0x03);
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if (prelen) {
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prelen = 4-prelen;
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set_link(n, (vm_offset_t)ptr, prelen, SFAS_CHAIN_BUMP);
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ptr += prelen;
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len -= prelen;
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}
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lastpa = 0;
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while(len > 3) {
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pa = kvtop(ptr);
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max_t = NBPG - (pa & PGOFSET);
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if (max_t > len)
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max_t = len;
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max_t &= ~3;
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if (lastpa == pa)
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sc->sc_chain[n-1].len += max_t;
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else
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set_link(n, pa, max_t, SFAS_CHAIN_DMA);
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lastpa = pa+max_t;
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ptr += max_t;
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len -= max_t;
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}
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if (len)
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set_link(n, (vm_offset_t)ptr, len, SFAS_CHAIN_BUMP);
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}
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return(n);
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}
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/* Turn on/off led */
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void
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flsc_led(sc, mode)
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struct sfas_softc *sc;
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int mode;
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{
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struct flsc_specific *spec;
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flsc_regmap_p rp;
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spec = sc->sc_spec;
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rp = (flsc_regmap_p)sc->sc_fas;
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if (mode) {
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sc->sc_led_status++;
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spec->portbits |= FLSC_PB_LED;
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*rp->hardbits = spec->portbits;
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} else {
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if (sc->sc_led_status)
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sc->sc_led_status--;
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if (!sc->sc_led_status) {
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spec->portbits &= ~FLSC_PB_LED;
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*rp->hardbits = spec->portbits;
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}
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}
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}
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