331 lines
9.3 KiB
C
331 lines
9.3 KiB
C
/* $NetBSD: fpu_fscale.c,v 1.6 1996/10/13 03:19:14 christos Exp $ */
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/*
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* Copyright (c) 1995 Ken Nakata
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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* 4. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Gordon Ross
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* FSCALE - separated from the other type0 arithmetic instructions
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* for performance reason; maybe unnecessary, but FSCALE assumes
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* the source operand be an integer. It performs type conversion
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* only if the source operand is *not* an integer.
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*/
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#include <sys/types.h>
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#include <sys/signal.h>
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#include <sys/systm.h>
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#include <machine/frame.h>
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#include "fpu_emulate.h"
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int
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fpu_emul_fscale(fe, insn)
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struct fpemu *fe;
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struct instruction *insn;
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{
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struct frame *frame;
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u_int *fpregs;
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int word1, sig;
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int regnum, format;
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int scale, sign, exp;
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u_int m0, m1;
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u_int buf[3], fpsr;
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int flags;
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char regname;
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scale = sig = 0;
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frame = fe->fe_frame;
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fpregs = &(fe->fe_fpframe->fpf_regs[0]);
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/* clear all exceptions and conditions */
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fpsr = fe->fe_fpsr & ~FPSR_EXCP & ~FPSR_CCB;
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if (fpu_debug_level & DL_FSCALE) {
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printf(" fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n", fpsr, fe->fe_fpcr);
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}
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word1 = insn->is_word1;
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format = (word1 >> 10) & 7;
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regnum = (word1 >> 7) & 7;
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fe->fe_fpcr &= FPCR_ROUND;
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fe->fe_fpcr |= FPCR_ZERO;
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/* get the source operand */
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if ((word1 & 0x4000) == 0) {
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if (fpu_debug_level & DL_FSCALE) {
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printf(" fpu_emul_fscale: FP%d op FP%d => FP%d\n",
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format, regnum, regnum);
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}
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/* the operand is an FP reg */
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if (fpu_debug_level & DL_FSCALE) {
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printf(" fpu_emul_scale: src opr FP%d=%08x%08x%08x\n",
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format, fpregs[format*3], fpregs[format*3+1],
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fpregs[format*3+2]);
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}
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fpu_explode(fe, &fe->fe_f2, FTYPE_EXT, &fpregs[format * 3]);
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fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf);
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} else {
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/* the operand is in memory */
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if (format == FTYPE_DBL) {
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insn->is_datasize = 8;
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} else if (format == FTYPE_SNG || format == FTYPE_LNG) {
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insn->is_datasize = 4;
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} else if (format == FTYPE_WRD) {
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insn->is_datasize = 2;
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} else if (format == FTYPE_BYT) {
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insn->is_datasize = 1;
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} else if (format == FTYPE_EXT) {
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insn->is_datasize = 12;
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} else {
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/* invalid or unsupported operand format */
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sig = SIGFPE;
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return sig;
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}
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/* Get effective address. (modreg=opcode&077) */
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sig = fpu_decode_ea(frame, insn, &insn->is_ea0, insn->is_opcode);
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if (sig) {
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if (fpu_debug_level & DL_FSCALE) {
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printf(" fpu_emul_fscale: error in decode_ea\n");
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}
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return sig;
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}
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if (fpu_debug_level & DL_FSCALE) {
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printf(" fpu_emul_fscale: addr mode = ");
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flags = insn->is_ea0.ea_flags;
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regname = (insn->is_ea0.ea_regnum & 8) ? 'a' : 'd';
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if (flags & EA_DIRECT) {
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printf("%c%d\n", regname, insn->is_ea0.ea_regnum & 7);
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} else if (insn->is_ea0.ea_flags & EA_PREDECR) {
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printf("%c%d@-\n", regname, insn->is_ea0.ea_regnum & 7);
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} else if (insn->is_ea0.ea_flags & EA_POSTINCR) {
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printf("%c%d@+\n", regname, insn->is_ea0.ea_regnum & 7);
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} else if (insn->is_ea0.ea_flags & EA_OFFSET) {
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printf("%c%d@(%d)\n", regname, insn->is_ea0.ea_regnum & 7,
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insn->is_ea0.ea_offset);
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} else if (insn->is_ea0.ea_flags & EA_INDEXED) {
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printf("%c%d@(...)\n", regname, insn->is_ea0.ea_regnum & 7);
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} else if (insn->is_ea0.ea_flags & EA_ABS) {
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printf("0x%08x\n", insn->is_ea0.ea_absaddr);
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} else if (insn->is_ea0.ea_flags & EA_PC_REL) {
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printf("pc@(%d)\n", insn->is_ea0.ea_offset);
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} else if (flags & EA_IMMED) {
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printf("#0x%08x%08x%08x\n",
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insn->is_ea0.ea_immed[0], insn->is_ea0.ea_immed[1],
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insn->is_ea0.ea_immed[2]);
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} else {
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printf("%c%d@\n", regname, insn->is_ea0.ea_regnum & 7);
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}
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}
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fpu_load_ea(frame, insn, &insn->is_ea0, (char*)buf);
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if (fpu_debug_level & DL_FSCALE) {
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printf(" fpu_emul_fscale: src = %08x%08x%08x, siz = %d\n",
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buf[0], buf[1], buf[2], insn->is_datasize);
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}
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if (format == FTYPE_LNG) {
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/* nothing */
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} else if (format == FTYPE_WRD) {
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/* sign-extend */
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scale = buf[0] & 0xffff;
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if (scale & 0x8000) {
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scale |= 0xffff0000;
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}
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} else if (format == FTYPE_BYT) {
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/* sign-extend */
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scale = buf[0] & 0xff;
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if (scale & 0x80) {
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scale |= 0xffffff00;
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}
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} else if (format == FTYPE_DBL || format == FTYPE_SNG ||
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format == FTYPE_EXT) {
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fpu_explode(fe, &fe->fe_f2, format, buf);
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fpu_implode(fe, &fe->fe_f2, FTYPE_LNG, buf);
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}
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/* make it look like we've got an FP oprand */
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fe->fe_f2.fp_class = (buf[0] == 0) ? FPC_ZERO : FPC_NUM;
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}
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/* assume there's no exception */
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sig = 0;
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/* it's barbaric but we're going to operate directly on
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* the dst operand's bit pattern */
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sign = fpregs[regnum * 3] & 0x80000000;
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exp = (fpregs[regnum * 3] & 0x7fff0000) >> 16;
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m0 = fpregs[regnum * 3 + 1];
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m1 = fpregs[regnum * 3 + 2];
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switch (fe->fe_f2.fp_class) {
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case FPC_SNAN:
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fpsr |= FPSR_SNAN;
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case FPC_QNAN:
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/* dst = NaN */
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exp = 0x7fff;
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m0 = m1 = 0xffffffff;
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break;
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case FPC_ZERO:
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case FPC_NUM:
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if ((0 < exp && exp < 0x7fff) ||
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(exp == 0 && (m0 | m1) != 0)) {
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/* normal or denormal */
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exp += scale;
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if (exp < 0) {
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/* underflow */
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u_int grs; /* guard, round and sticky */
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exp = 0;
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grs = m1 << (32 + exp);
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m1 = m0 << (32 + exp) | m1 >> -exp;
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m0 >>= -exp;
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if (grs != 0) {
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fpsr |= FPSR_INEX2;
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switch (fe->fe_fpcr & 0x30) {
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case FPCR_MINF:
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if (sign != 0) {
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if (++m1 == 0 &&
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++m0 == 0) {
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m0 = 0x80000000;
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exp++;
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}
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}
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break;
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case FPCR_NEAR:
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if (grs == 0x80000000) {
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/* tie */
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if ((m1 & 1) &&
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++m1 == 0 &&
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++m0 == 0) {
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m0 = 0x80000000;
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exp++;
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}
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} else if (grs & 0x80000000) {
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if (++m1 == 0 &&
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++m0 == 0) {
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m0 = 0x80000000;
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exp++;
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}
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}
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break;
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case FPCR_PINF:
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if (sign == 0) {
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if (++m1 == 0 &&
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++m0 == 0) {
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m0 = 0x80000000;
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exp++;
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}
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}
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break;
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case FPCR_ZERO:
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break;
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}
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}
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if (exp == 0 && (m0 & 0x80000000) == 0) {
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fpsr |= FPSR_UNFL;
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if ((m0 | m1) == 0) {
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fpsr |= FPSR_ZERO;
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}
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}
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} else if (exp >= 0x7fff) {
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/* overflow --> result = Inf */
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/* but first, try to normalize in case it's an unnormalized */
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while ((m0 & 0x80000000) == 0) {
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exp--;
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m0 = (m0 << 1) | (m1 >> 31);
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m1 = m1 << 1;
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}
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/* if it's still too large, then return Inf */
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if (exp >= 0x7fff) {
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exp = 0x7fff;
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m0 = m1 = 0;
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fpsr |= FPSR_OVFL | FPSR_INF;
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}
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} else if ((m0 & 0x80000000) == 0) {
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/*
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* it's a denormal; we try to normalize but
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* result may and may not be a normal.
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*/
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while (exp > 0 && (m0 & 0x80000000) == 0) {
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exp--;
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m0 = (m0 << 1) | (m1 >> 31);
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m1 = m1 << 1;
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}
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if ((m0 & 0x80000000) == 0) {
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fpsr |= FPSR_UNFL;
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}
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} /* exp in range and mantissa normalized */
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} else if (exp == 0 && m0 == 0 && m1 == 0) {
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/* dst is Zero */
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fpsr |= FPSR_ZERO;
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} /* else we know exp == 0x7fff */
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else if ((m0 | m1) == 0) {
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fpsr |= FPSR_INF;
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} else if ((m0 & 0x40000000) == 0) {
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/* a signaling NaN */
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fpsr |= FPSR_NAN | FPSR_SNAN;
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} else {
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/* a quiet NaN */
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fpsr |= FPSR_NAN;
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}
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break;
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case FPC_INF:
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/* dst = NaN */
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exp = 0x7fff;
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m0 = m1 = 0xffffffff;
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fpsr |= FPSR_OPERR | FPSR_NAN;
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break;
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default:
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#ifdef DEBUG
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panic(" fpu_emul_fscale: invalid fp class");
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#endif
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break;
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}
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/* store the result */
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fpregs[regnum * 3] = sign | (exp << 16);
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fpregs[regnum * 3 + 1] = m0;
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fpregs[regnum * 3 + 2] = m1;
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if (sign) {
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fpsr |= FPSR_NEG;
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}
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/* update fpsr according to the result of operation */
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fe->fe_fpframe->fpf_fpsr = fe->fe_fpsr = fpsr;
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if (fpu_debug_level & DL_FSCALE) {
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printf(" fpu_emul_fscale: FPSR = %08x, FPCR = %08x\n",
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fe->fe_fpsr, fe->fe_fpcr);
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}
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return (fpsr & fe->fe_fpcr & FPSR_EXCP) ? SIGFPE : sig;
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}
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