119 lines
3.6 KiB
ArmAsm
119 lines
3.6 KiB
ArmAsm
/* $NetBSD: spl.S,v 1.8 2008/04/27 18:58:44 matt Exp $ */
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/*
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* Copyright (c) 1996-1998 Mark Brinicombe.
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* Copyright (c) Brini.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Mark Brinicombe
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* for the NetBSD Project.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* spl routines
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*
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* Created : 01/03/96
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*/
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#include "assym.h"
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#include <arm/arm32/psl.h>
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#include <machine/asm.h>
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#include <machine/cpu.h>
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RCSID("$NetBSD: spl.S,v 1.8 2008/04/27 18:58:44 matt Exp $")
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.text
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.align 0
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.Lcpu_info_store:
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.word _C_LABEL(cpu_info_store)
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ENTRY(raisespl)
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mov r3, r0 /* Save the new value */
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ldr r1, .Lcpu_info_store /* Get the current spl level */
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ldr r0, [r1, #CI_CPL]
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cmp r3, r0
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RETc(le)
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stmfd sp!, {r0, r1, r4, lr} /* Preserve registers */
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/* Disable interrupts */
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mrs r4, cpsr_all
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orr r2, r4, #(I32_bit)
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msr cpsr_c, r2
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str r3, [r1, #CI_CPL] /* Store the new spl level */
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bl _C_LABEL(irq_setmasks) /* Update the actual masks */
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msr cpsr_c, r4 /* Restore interrupts */
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ldmfd sp!, {r0, r1, r4, pc} /* Restore registers */
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ENTRY(lowerspl)
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mov r3, r0 /* Save the new value */
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ldr r1, .Lcpu_info_store /* Get the current spl level */
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ldr r0, [r1, #CI_CPL]
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cmp r3, r0
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RETc(ge)
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stmfd sp!, {r0, r1, r4, lr} /* Preserve registers */
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/* Disable interrupts */
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mrs r4, cpsr_all
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orr r2, r4, #(I32_bit)
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msr cpsr_c, r2
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str r3, [r1, #CI_CPL] /* Store the new spl level */
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bl _C_LABEL(irq_setmasks) /* Update the actual masks */
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msr cpsr_all, r4
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#ifdef __HAVE_FAST_SOFTINTS
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bl _C_LABEL(dosoftints) /* Process any pending soft ints */
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#endif
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ldmfd sp!, {r0, r1, r4, pc} /* restore registers */
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ENTRY(splx)
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mov r3, r0 /* Save the new value */
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ldr r1, .Lcpu_info_store /* Get the current spl level */
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ldr r0, [r1, #CI_CPL]
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cmp r3, r0
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RETc(eq)
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stmfd sp!, {r0, r1, r4, lr}
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/* Disable interrupts */
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mrs r4, cpsr_all
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orr r2, r4, #(I32_bit)
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msr cpsr_c, r2
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str r3, [r1, #CI_CPL] /* Store the new spl level */
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bl _C_LABEL(irq_setmasks) /* Update the actual masks */
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#ifdef __HAVE_FAST_SOFTINTS
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bl _C_LABEL(dosoftints) /* Process any pending soft ints */
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#endif
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msr cpsr_c, r4
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ldmfd sp!, {r0, r1, r4, pc}
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