356 lines
9.2 KiB
C
356 lines
9.2 KiB
C
/* $NetBSD: esp.c,v 1.10 1999/04/08 04:46:41 gwr Exp $ */
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/*-
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jeremy Cooper and Gordon W. Ross
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* "Front end" glue for the ncr53c9x chip, formerly known as the
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* Emulex SCSI Processor (ESP) which is what we actually have.
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_message.h>
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#include <machine/autoconf.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <sun3/dev/dmareg.h>
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#include <sun3/dev/dmavar.h>
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#define ESP_REG_SIZE (12*4)
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struct esp_softc {
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struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
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volatile u_char *sc_reg; /* the registers */
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struct dma_softc *sc_dma; /* pointer to my dma */
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};
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static int espmatch __P((struct device *, struct cfdata *, void *));
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static void espattach __P((struct device *, struct device *, void *));
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struct cfattach esp_ca = {
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sizeof(struct esp_softc), espmatch, espattach
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};
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static struct scsipi_device esp_dev = {
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NULL, /* Use default error handler */
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NULL, /* have a queue, served by this */
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NULL, /* have no async handler */
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NULL, /* Use default 'done' routine */
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};
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/*
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* Functions and the switch for the MI code.
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*/
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static u_char esp_read_reg __P((struct ncr53c9x_softc *, int));
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static void esp_write_reg __P((struct ncr53c9x_softc *, int, u_char));
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static int esp_dma_isintr __P((struct ncr53c9x_softc *));
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static void esp_dma_reset __P((struct ncr53c9x_softc *));
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static int esp_dma_intr __P((struct ncr53c9x_softc *));
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static int esp_dma_setup __P((struct ncr53c9x_softc *, caddr_t *,
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size_t *, int, size_t *));
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static void esp_dma_go __P((struct ncr53c9x_softc *));
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static void esp_dma_stop __P((struct ncr53c9x_softc *));
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static int esp_dma_isactive __P((struct ncr53c9x_softc *));
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static struct ncr53c9x_glue esp_glue = {
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esp_read_reg,
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esp_write_reg,
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esp_dma_isintr,
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esp_dma_reset,
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esp_dma_intr,
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esp_dma_setup,
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esp_dma_go,
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esp_dma_stop,
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esp_dma_isactive,
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NULL, /* gl_clear_latched_intr */
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};
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static int
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espmatch(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct confargs *ca = aux;
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/*
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* Check for the esp registers.
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*/
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if (bus_peek(ca->ca_bustype,
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ca->ca_paddr + (NCR_STAT * 4), 1) == -1)
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return (0);
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/* If default ipl, fill it in. */
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if (ca->ca_intpri == -1)
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ca->ca_intpri = 2;
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return (1);
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}
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static void
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espattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct confargs *ca = aux;
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struct esp_softc *esc = (void *)self;
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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/*
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* Set up glue for MI code early; we use some of it here.
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*/
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sc->sc_glue = &esp_glue;
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/*
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* Map in the ESP registers.
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*/
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esc->sc_reg =
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bus_mapin(ca->ca_bustype, ca->ca_paddr, ESP_REG_SIZE);
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/* Other settings */
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sc->sc_id = 7;
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sc->sc_freq = 20; /* The 3/80 esp runs at 20 Mhz */
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/*
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* Hook up the DMA driver.
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*/
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esc->sc_dma = espdmafind(sc->sc_dev.dv_unit);
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esc->sc_dma->sc_esp = sc; /* Point back to us */
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/*
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* XXX More of this should be in ncr53c9x_attach(), but
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* XXX should we really poke around the chip that much in
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* XXX the MI code? Think about this more...
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*/
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/*
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* It is necessary to try to load the 2nd config register here,
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* to find out what rev the esp chip is, else the ncr53c9x_reset
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* will not set up the defaults correctly.
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*/
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_RPE;
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sc->sc_cfg3 = NCRCFG3_CDB;
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NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
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if ((NCR_READ_REG(sc, NCR_CFG2) & ~NCRCFG2_RSVD) !=
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(NCRCFG2_SCSI2 | NCRCFG2_RPE)) {
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sc->sc_rev = NCR_VARIANT_ESP100;
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} else {
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sc->sc_cfg2 = NCRCFG2_SCSI2;
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NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
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sc->sc_cfg3 = 0;
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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sc->sc_cfg3 = (NCRCFG3_CDB | NCRCFG3_FCLK);
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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if (NCR_READ_REG(sc, NCR_CFG3) !=
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(NCRCFG3_CDB | NCRCFG3_FCLK)) {
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sc->sc_rev = NCR_VARIANT_ESP100A;
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} else {
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/* NCRCFG2_FE enables > 64K transfers */
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sc->sc_cfg2 |= NCRCFG2_FE;
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sc->sc_cfg3 = 0;
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NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
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sc->sc_rev = NCR_VARIANT_ESP200;
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}
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}
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/*
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* XXX minsync and maxxfer _should_ be set up in MI code,
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* XXX but it appears to have some dependency on what sort
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* XXX of DMA we're hooked up to, etc.
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*/
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/*
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* This is the value used to start sync negotiations
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* Note that the NCR register "SYNCTP" is programmed
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* in "clocks per byte", and has a minimum value of 4.
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* The SCSI period used in negotiation is one-fourth
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* of the time (in nanoseconds) needed to transfer one byte.
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* Since the chip's clock is given in MHz, we have the following
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* formula: 4 * period = (1000 / freq) * 4
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*/
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sc->sc_minsync = 1000 / sc->sc_freq;
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/*
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* Alas, we must now modify the value a bit, because it's
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* only valid when can switch on FASTCLK and FASTSCSI bits
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* in config register 3...
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*/
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switch (sc->sc_rev) {
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case NCR_VARIANT_ESP100:
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sc->sc_maxxfer = 64 * 1024;
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sc->sc_minsync = 0; /* No synch on old chip? */
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break;
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case NCR_VARIANT_ESP100A:
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sc->sc_maxxfer = 64 * 1024;
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/* Min clocks/byte is 5 */
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sc->sc_minsync = ncr53c9x_cpb2stp(sc, 5);
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break;
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case NCR_VARIANT_ESP200:
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sc->sc_maxxfer = 16 * 1024 * 1024;
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/* XXX - do actually set FAST* bits */
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break;
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}
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/* and the interuppts */
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isr_add_autovect((void*)ncr53c9x_intr, sc, ca->ca_intpri);
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evcnt_attach(&sc->sc_dev, "intr", &sc->sc_intrcnt);
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/* Do the common parts of attachment. */
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sc->sc_adapter.scsipi_cmd = ncr53c9x_scsi_cmd;
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sc->sc_adapter.scsipi_minphys = minphys;
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ncr53c9x_attach(sc, &esp_dev);
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#if 0
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/* XXX - This doesn't work yet. Not sure why... */
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/* Turn on target selection using the `dma' method */
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ncr53c9x_dmaselect = 1; /* XXX - OK? */
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#endif
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}
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/*
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* Glue functions.
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*/
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u_char
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esp_read_reg(sc, reg)
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struct ncr53c9x_softc *sc;
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int reg;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return (esc->sc_reg[reg * 4]);
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}
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void
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esp_write_reg(sc, reg, val)
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struct ncr53c9x_softc *sc;
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int reg;
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u_char val;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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esc->sc_reg[reg * 4] = val;
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}
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int
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esp_dma_isintr(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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u_int32_t csr;
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csr = DMACSR(esc->sc_dma);
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return (csr & (D_INT_PEND|D_ERR_PEND));
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}
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void
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esp_dma_reset(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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dma_reset(esc->sc_dma);
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}
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int
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esp_dma_intr(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return (espdmaintr(esc->sc_dma));
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}
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int
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esp_dma_setup(sc, addr, len, datain, dmasize)
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struct ncr53c9x_softc *sc;
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caddr_t *addr;
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size_t *len;
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int datain;
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size_t *dmasize;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return (dma_setup(esc->sc_dma, addr, len, datain, dmasize));
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}
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void
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esp_dma_go(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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/* Start DMA */
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DMACSR(esc->sc_dma) |= D_EN_DMA;
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esc->sc_dma->sc_active = 1;
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}
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void
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esp_dma_stop(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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DMACSR(esc->sc_dma) &= ~D_EN_DMA;
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}
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int
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esp_dma_isactive(sc)
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struct ncr53c9x_softc *sc;
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{
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struct esp_softc *esc = (struct esp_softc *)sc;
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return (esc->sc_dma->sc_active);
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}
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