65363da25e
Tree structure: - sys/arch/sh3: sh3 generic code As commented, in-chip device drivers are put into sys/arch/sh3/dev. - sys/arch/evbsh3: sh3 evaluation boards (pure sh3 CPU, no fancy external HW) - sys/arch/mmeye: Brains mmEye, www.brains.co.jp MI source code includes couple of #ifdef for sh3-coff support. (sh3 uses coff or elf) Needs some more improvements, especialy in sys/arch/sh3/conf/files.sh3, to compile the tree (due to last minute tree structure change).
203 lines
6.2 KiB
C
203 lines
6.2 KiB
C
/* $NetBSD: shpcicvar.h,v 1.1 1999/09/13 10:31:13 itojun Exp $ */
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/*
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* Copyright (c) 1997 Marc Horowitz. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Marc Horowitz.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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struct proc;
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struct shpcic_event {
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SIMPLEQ_ENTRY(shpcic_event) pe_q;
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int pe_type;
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};
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/* pe_type */
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#define SHPCIC_EVENT_INSERTION 0
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#define SHPCIC_EVENT_REMOVAL 1
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struct shpcic_handle {
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struct shpcic_softc *sc;
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int vendor;
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int sock;
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int flags;
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int laststate;
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int memalloc;
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struct {
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bus_addr_t addr;
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bus_size_t size;
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long offset;
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int kind;
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} mem[SHPCIC_MEM_WINS];
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int ioalloc;
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struct {
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bus_addr_t addr;
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bus_size_t size;
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int width;
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} io[SHPCIC_IO_WINS];
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int ih_irq;
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struct device *pcmcia;
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int shutdown;
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struct proc *event_thread;
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SIMPLEQ_HEAD(, shpcic_event) events;
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};
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/* These four lines are MMTA specific */
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#define SHPCIC_IRQ1 10
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#define SHPCIC_IRQ2 9
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#define SHPCIC_SLOT1_ADDR 0xb8000000
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#define SHPCIC_SLOT2_ADDR 0xb9000000
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#define SHPCIC_FLAG_SOCKETP 0x0001
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#define SHPCIC_FLAG_CARDP 0x0002
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#define SHPCIC_LASTSTATE_PRESENT 0x0002
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#define SHPCIC_LASTSTATE_HALF 0x0001
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#define SHPCIC_LASTSTATE_EMPTY 0x0000
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#define C0SA SHPCIC_CHIP0_BASE+SHPCIC_SOCKETA_INDEX
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#define C0SB SHPCIC_CHIP0_BASE+SHPCIC_SOCKETB_INDEX
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#define C1SA SHPCIC_CHIP1_BASE+SHPCIC_SOCKETA_INDEX
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#define C1SB SHPCIC_CHIP1_BASE+SHPCIC_SOCKETB_INDEX
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/*
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* This is sort of arbitrary. It merely needs to be "enough". It can be
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* overridden in the conf file, anyway.
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*/
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#define SHPCIC_MEM_PAGES 4
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#define SHPCIC_MEMSIZE SHPCIC_MEM_PAGES*SHPCIC_MEM_PAGESIZE
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#define SHPCIC_NSLOTS 4
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#define SHPCIC_WINS 5
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#define SHPCIC_IOWINS 2
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struct shpcic_softc {
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struct device dev;
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bus_space_tag_t memt;
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bus_space_handle_t memh;
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bus_space_tag_t iot;
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bus_space_handle_t ioh;
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/* XXX isa_chipset_tag_t, pci_chipset_tag_t, etc. */
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void *intr_est;
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pcmcia_chipset_tag_t pct;
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/* this needs to be large enough to hold PCIC_MEM_PAGES bits */
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int subregionmask;
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#define SHPCIC_MAX_MEM_PAGES (8 * sizeof(int))
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/* used by memory window mapping functions */
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bus_addr_t membase;
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/*
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* used by io window mapping functions. These can actually overlap
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* with another pcic, since the underlying extent mapper will deal
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* with individual allocations. This is here to deal with the fact
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* that different busses have different real widths (different pc
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* hardware seems to use 10 or 12 bits for the I/O bus).
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*/
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bus_addr_t iobase;
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bus_addr_t iosize;
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int irq;
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void *ih;
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struct shpcic_handle handle[SHPCIC_NSLOTS];
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};
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int shpcic_ident_ok __P((int));
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int shpcic_vendor __P((struct shpcic_handle *));
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char *shpcic_vendor_to_string __P((int));
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void shpcic_attach __P((struct shpcic_softc *));
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void shpcic_attach_sockets __P((struct shpcic_softc *));
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int shpcic_intr __P((void *arg));
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static inline int shpcic_read __P((struct shpcic_handle *, int));
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static inline void shpcic_write __P((struct shpcic_handle *, int, int));
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int shpcic_chip_mem_alloc __P((pcmcia_chipset_handle_t, bus_size_t,
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struct pcmcia_mem_handle *));
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void shpcic_chip_mem_free __P((pcmcia_chipset_handle_t,
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struct pcmcia_mem_handle *));
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int shpcic_chip_mem_map __P((pcmcia_chipset_handle_t, int, bus_addr_t,
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bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *));
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void shpcic_chip_mem_unmap __P((pcmcia_chipset_handle_t, int));
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int shpcic_chip_io_alloc __P((pcmcia_chipset_handle_t, bus_addr_t,
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bus_size_t, bus_size_t, struct pcmcia_io_handle *));
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void shpcic_chip_io_free __P((pcmcia_chipset_handle_t,
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struct pcmcia_io_handle *));
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int shpcic_chip_io_map __P((pcmcia_chipset_handle_t, int, bus_addr_t,
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bus_size_t, struct pcmcia_io_handle *, int *));
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void shpcic_chip_io_unmap __P((pcmcia_chipset_handle_t, int));
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void shpcic_chip_socket_enable __P((pcmcia_chipset_handle_t));
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void shpcic_chip_socket_disable __P((pcmcia_chipset_handle_t));
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static __inline int shpcic_read __P((struct shpcic_handle *, int));
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static __inline int
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shpcic_read(h, idx)
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struct shpcic_handle *h;
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int idx;
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{
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static int prev_idx = 0;
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if (idx == -1){
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idx = prev_idx;
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}
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prev_idx = idx;
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return (bus_space_read_stream_2(h->sc->iot, h->sc->ioh, idx));
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}
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static __inline void shpcic_write __P((struct shpcic_handle *, int, int));
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static __inline void
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shpcic_write(h, idx, data)
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struct shpcic_handle *h;
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int idx;
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int data;
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{
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static int prev_idx;
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if (idx == -1){
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idx = prev_idx;
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}
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prev_idx = idx;
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bus_space_write_stream_2(h->sc->iot, h->sc->ioh, idx, (data));
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}
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void *pcic_shb_chip_intr_establish __P((pcmcia_chipset_handle_t,
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struct pcmcia_function *, int, int (*) (void *), void *));
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void pcic_shb_chip_intr_disestablish __P((pcmcia_chipset_handle_t, void *));
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void pcic_shb_bus_width_probe __P((struct shpcic_softc *, bus_space_tag_t,
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bus_space_handle_t, bus_addr_t, u_int32_t));
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