105 lines
3.6 KiB
C
105 lines
3.6 KiB
C
/* $NetBSD: intrdefs.h,v 1.3 2008/04/28 20:23:25 martin Exp $ */
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/*-
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Takayoshi Kochi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IA64_INTRDEFS_H_
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#define _IA64_INTRDEFS_H_
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/* Interrupt priority levels. */
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#define IPL_NONE 0x0 /* nothing */
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#define IPL_SOFTCLOCK 0x1 /* timeouts */
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#define IPL_SOFTBIO 0x2 /* block I/O passdown */
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#define IPL_SOFTNET 0x3 /* protocol stacks */
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#define IPL_SOFTSERIAL 0x4 /* serial passdown */
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#define IPL_VM 0x5 /* low I/O, memory allocation */
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#define IPL_SCHED 0x6 /* medium I/O, scheduler, clock */
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#define IPL_HIGH 0x7 /* high I/O, statclock, IPIs */
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#define NIPL 8
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/* Interrupt sharing types. */
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#define IST_NONE 0 /* none */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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/*
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* Local APIC masks and software interrupt masks, in order
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* of priority. Must not conflict with SIR_* below.
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*/
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#define LIR_IPI 31
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#define LIR_TIMER 30
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/*
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* XXX These should be lowest numbered, but right now would
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* conflict with the legacy IRQs. Their current position
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* means that soft interrupt take priority over hardware
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* interrupts when lowering the priority level!
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*/
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#define SIR_SERIAL 29
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#define SIR_NET 28
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#define SIR_BIO 27
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#define SIR_CLOCK 26
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/*
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* Maximum # of interrupt sources per CPU. 32 to fit in one word.
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* ioapics can theoretically produce more, but it's not likely to
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* happen. For multiple ioapics, things can be routed to different
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* CPUs.
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*/
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#define MAX_INTR_SOURCES 32
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#define NUM_LEGACY_IRQS 16
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/*
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* Low and high boundaries between which interrupt gates will
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* be allocated in the IDT.
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*/
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#define IDT_INTR_LOW (0x20 + NUM_LEGACY_IRQS)
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#define IDT_INTR_HIGH 0xef
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#define X86_IPI_HALT 0x00000001
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#define X86_IPI_MICROSET 0x00000002
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#define X86_IPI_FLUSH_FPU 0x00000004
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#define X86_IPI_SYNCH_FPU 0x00000008
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#define X86_IPI_MTRR 0x00000010
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#define X86_IPI_GDT 0x00000020
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#define X86_IPI_WRITE_MSR 0x00000040
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#define X86_IPI_ACPI_CPU_SLEEP 0x00000080
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#define X86_NIPI 8
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#define X86_IPI_NAMES { "halt IPI", "timeset IPI", "FPU flush IPI", \
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"FPU synch IPI", "MTRR update IPI", \
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"GDT update IPI", "MSR write IPI", \
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"ACPI CPU sleep IPI" }
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#define IREENT_MAGIC 0x18041969
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#endif /* _IA64_INTRDEFS_H_ */
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