118 lines
5.0 KiB
C
118 lines
5.0 KiB
C
/* $NetBSD: dma.h,v 1.1 2000/12/24 09:25:28 ur Exp $ */
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/* $OpenBSD: dma.h,v 1.3 1997/04/19 17:19:51 pefo Exp $ */
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/*
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* Copyright (c) 1996 Per Fogelstrom
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Per Fogelstrom.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Hardware dma registers.
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*/
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typedef volatile struct {
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int32_t dma_mode;
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int32_t pad1;
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int32_t dma_enab;
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int32_t pad2;
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int32_t dma_count;
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int32_t pad3;
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int32_t dma_addr;
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int32_t pad4;
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} DmaReg, *pDmaReg;
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#define R4030_DMA_MODE_40NS 0x00 /* Device dma timing */
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#define R4030_DMA_MODE_80NS 0x01 /* Device dma timing */
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#define R4030_DMA_MODE_120NS 0x02 /* Device dma timing */
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#define R4030_DMA_MODE_160NS 0x03 /* Device dma timing */
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#define R4030_DMA_MODE_200NS 0x04 /* Device dma timing */
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#define R4030_DMA_MODE_240NS 0x05 /* Device dma timing */
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#define R4030_DMA_MODE_280NS 0x06 /* Device dma timing */
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#define R4030_DMA_MODE_320NS 0x07 /* Device dma timing */
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#define R4030_DMA_MODE_8 0x08 /* Device 8 bit */
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#define R4030_DMA_MODE_16 0x10 /* Device 16 bit */
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#define R4030_DMA_MODE_32 0x18 /* Device 32 bit */
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#define R4030_DMA_MODE_INT 0x20 /* Interrupt when done */
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#define R4030_DMA_MODE_BURST 0x40 /* Burst mode (Rev 2 only) */
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#define R4030_DMA_MODE_FAST 0x80 /* Fast dma cycle (Rev 2 only) */
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#define R4030_DMA_MODE 0xff /* Mode register bits */
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#define DMA_DIR_WRITE 0x100 /* Software direction status */
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#define DMA_DIR_READ 0x000 /* Software direction status */
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#define R4030_DMA_ENAB_RUN 0x01 /* Enable dma */
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#define R4030_DMA_ENAB_READ 0x00 /* Read from device */
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#define R4030_DMA_ENAB_WRITE 0x02 /* Write to device */
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#define R4030_DMA_ENAB_TC_IE 0x100 /* Terminal count int enable */
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#define R4030_DMA_ENAB_ME_IE 0x200 /* Memory error int enable */
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#define R4030_DMA_ENAB_TL_IE 0x400 /* Translation limit int enable */
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#define R4030_DMA_COUNT_MASK 0x000fffff /* Byte count mask */
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/*
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* Structure used to control dma.
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*/
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typedef struct dma_softc {
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struct device sc_dev; /* use as a device */
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struct esp_softc *sc_esp;
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bus_addr_t dma_va; /* Viritual address for transfer */
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int mode; /* Mode register value and direction */
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jazz_dma_pte_t *pte_base; /* Pointer to dma tlb array */
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int pte_size; /* Size of pte allocated pte array */
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pDmaReg dma_reg; /* Pointer to dma registers */
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int sc_active; /* Active flag */
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void (*reset)(struct dma_softc *); /* Reset routine pointer */
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void (*enintr)(struct dma_softc *); /* Int enab routine pointer */
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void (*map)(struct dma_softc *, char *, size_t, int);
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/* Map a dma viritual area */
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void (*start)(struct dma_softc *, caddr_t, size_t, int);
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/* Start routine pointer */
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int (*isintr)(struct dma_softc *); /* Int check routine pointer */
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int (*intr)(struct dma_softc *); /* Interrupt routine pointer */
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void (*end)(struct dma_softc *); /* Interrupt routine pointer */
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} dma_softc_t;
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#define DMA_TO_DEV 0
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#define DMA_FROM_DEV 1
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#define DMA_RESET(r) ((r->reset)(r))
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#define DMA_START(a, b, c, d) ((a->start)(a, b, c, d))
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#define DMA_MAP(a, b, c, d) ((a->map)(a, b, c, d))
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#define DMA_INTR(r) ((r->intr)(r))
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#define DMA_DRAIN(r)
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#define DMA_END(r) ((r->end)(r))
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void picaDmaInit __P((void));
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void picaDmaTLBAlloc __P((dma_softc_t *));
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void picaDmaTLBFree __P((dma_softc_t *));
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void picaDmaMap __P((struct dma_softc *, char *, size_t, int));
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void picaDmaStart __P((struct dma_softc *, char *, size_t, int));
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void picaDmaFlush __P((struct dma_softc *, char *, size_t, int));
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void asc_dma_init __P((struct dma_softc *));
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void fdc_dma_init __P((struct dma_softc *));
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void sn_dma_init __P((struct dma_softc *, int));
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