173 lines
7.8 KiB
C
173 lines
7.8 KiB
C
/* $NetBSD: ka420.h,v 1.2 1998/06/07 18:34:09 ragge Exp $ */
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/*
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* Copyright (c) 1996 Ludd, University of Lule}, Sweden.
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* All rights reserved.
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*
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* This code is derived from software contributed to Ludd by Bertram Barth.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed at Ludd, University of
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* Lule}, Sweden and its contributors.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Definitions for I/O addresses of
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*
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* VAXstation 3100 models 30, 40 (PVAX)
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* MicroVAX 3100 models 10, 20 (Teammate II)
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* MicroVAX 3100 models 10e, 20e (Teammate II)
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* VAXstation 3100 models 38, 48 (PVAX rev#7)
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*/
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#define KA420_SIDEX 0x20040004 /* SID extension register */
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#define KA420_CH2_BASE 0x10000000 /* 2nd level cache data area */
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#define KA420_CH2_END 0x10007FFF
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#define KA420_CH2_SIZE 0x8000
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#define KA420_CT2_BASE 0x10010000 /* 2nd level cache tag area */
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#define KA420_CT2_END 0x10017FFF
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#define KA420_CT2_SIZE 0x8000
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#define KA420_CH2_CREG 0x20084000 /* 2nd level cache control register */
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#define KA420_CFGTST 0x20020000 /* Configuration and Test register */
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#define KA420_IORESET 0x20020000 /* I/O Reset register */
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#define KA420_ROM_BASE 0x20040000 /* System module ROM */
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#define KA420_ROM_END 0x2007FFFF
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#define KA420_ROM_SIZE 0x40000 /* ??? */
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#define KA420_IVN_BASE 0x20040020 /* Interrupt Vector Numbers */
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#define KA420_IVN_END 0x2004003F
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#define KA420_IVN_SIZE 0x20
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#define KA420_HLTCOD 0x20080000 /* Halt Code Register */
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#define KA420_MSER 0x20080004 /* Memory System Error register */
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#define KA420_MEAR 0x20080008 /* Memory Error Address register */
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#define KA420_INTMSK 0x2008000C /* Interrupt Mask register */
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#define KA420_VDCORG 0x2008000D /* Video Controller Origin Register */
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#define KA420_VDCSEL 0x2008000E /* Video Controller Select Register */
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#define KA420_INTREQ 0x2008000F /* Interrupt Request register */
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#define KA420_INTCLR 0x2008000F /* Interrupt Request clear register */
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#define KA420_CACR 0x20084000 /* L2 cache ctrl reg */
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/*
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* Other fixed addresses which should be mapped
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*/
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#define KA420_NWA_BASE 0x20090000 /* Network Address ROM */
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#define KA420_NWA_END 0x2009007F
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#define KA420_NWA_SIZE 0x80
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#define KA420_SER_BASE 0x200A0000 /* Serial line controller */
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#define KA420_SER_END 0x200A000F
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#define KA420_SER_SIZE 0x10
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#define KA420_WAT_BASE 0x200B0000 /* TOY clock and NV-RAM */
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#define KA420_WAT_END 0x200B00FF
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#define KA420_WAT_SIZE 0x100
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#define KA420_DKC_BASE 0x200C0000 /* Disk Controller Ports */
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#define KA420_DKC_END 0x200C0007
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#define KA420_DKC_SIZE 0x08
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#define KA420_SCS_BASE 0x200C0080 /* Tape (SCSI) Controller Chip */
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#define KA420_SCS_END 0x200C009F
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#define KA420_SCS_SIZE 0x20
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#define KA420_D16_BASE 0x200D0000 /* 16KB (compatibility) Data Buffer */
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#define KA420_D16_END 0x200D3FFF
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#define KA420_D16_SIZE 0x4000
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#define KA420_LAN_BASE 0x200E0000 /* LANCE chip registers */
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#define KA420_LAN_END 0x200E0007
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#define KA420_LAN_SIZE 0x08
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#define KA420_CUR_BASE 0x200F0000 /* Monochrome video cursor chip */
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#define KA420_CUR_END 0x200F0007
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#define KA420_CUR_SIZE 0x08
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#define KA420_DMA_BASE 0x202D0000 /* 128KB Data Buffer */
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#define KA420_DMA_END 0x202EFFFF
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#define KA420_DMA_SIZE 0x20000
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#define KA420_SCD_DADR 0x200C00A0 /* Tape(SCSI) DMA address register */
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#define KA420_SCD_DCNT 0x200C00C0 /* Tape(SCSI) DMA byte count reg. */
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#define KA420_SCD_DDIR 0x200C00C4 /* Tape(SCSI) DMA transfer direction */
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#define KA420_STC_MODE 0x200C00E0 /* Storage Controller Mode register */
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#define KA420_CUR_CMD 0x200F0000 /* Cursor Command Register */
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#define KA420_CUR_XPOS 0x200F0004 /* Cursor X position */
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#define KA420_CUR_YPOS 0x200F0008 /* Cursor Y position */
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#define KA420_CUR_XMIN1 0x200F000C /* Region 1 left edge */
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#define KA420_CUR_XMAX1 0x200F0010 /* Region 1 right edge */
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#define KA420_CUR_YMIN1 0x200F0014 /* Region 1 top edge */
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#define KA420_CUR_YMAX1 0x200F0018 /* Region 1 bottom edge */
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#define KA420_CUR_XMIN2 0x200F002C /* Region 2 left edge */
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#define KA420_CUR_XMAX2 0x200F0030 /* Region 2 right edge */
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#define KA420_CUR_YMIN2 0x200F0034 /* Region 2 top edge */
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#define KA420_CUR_YMAX2 0x200F0038 /* Region 2 bottom edge */
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/*
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* Clock-Chip data in NVRAM
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*/
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#define KA420_CPMBX 0x200B0038 /* Console Mailbox (1 byte) */
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#define KA420_CPFLG 0x200B003C /* Console Program Flags (1 byte) */
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#define KA420_LK201_ID 0x200B0040 /* Keyboard Variation (1 byte) */
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#define KA420_CONS_ID 0x200B0044 /* Console Device Type (1 byte) */
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#define KA420_SCR 0x200B0048 /* Console Scratch RAM */
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#define KA420_TEMP 0x200B0058 /* Used by System Firmware */
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#define KA420_BAT_CHK 0x200B0088 /* Battery Check Data */
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#define KA420_BOOTDEV 0x200B0098 /* Default Boot Device (4 bytes) */
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#define KA420_BOOTFLG 0x200B00A8 /* Default Boot Flags (4 bytes) */
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#define KA420_SCRLEN 0x200B00B8 /* Number of pages of SCR (1 byte) */
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#define KA420_SCSIPORT 0x200B00BC /* Tape Controller Port Data */
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#define KA420_RESERVED 0x200B00C0 /* Reserved (16 bytes) */
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/* Used bits in the CFGTST (20020000) register */
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#define KA420_CFG_STCMSK 0xc000 /* Storage controller mask */
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#define KA420_CFG_RB 0x0000 /* RB (ST506/SCSI) present */
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#define KA420_CFG_RD 0x4000 /* RD (SCSI/SCSI) present */
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#define KA420_CFG_NONE 0xc000 /* No storage ctlr present */
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#define KA420_CFG_MULTU 0x80 /* MicroVAX or VAXstation */
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#define KA420_CFG_CACHPR 0x40 /* Secondary cache present */
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#define KA420_CFG_L3CON 0x20 /* Console on line #3 of dc */
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#define KA420_CFG_CURTEST 0x10 /* Cursor Test (monochrom) */
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#define KA420_CFG_VIDOPT 0x08 /* Video option present */
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/* Primary cache bits (CADR, IPR 37) */
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#define KA420_CADR_S2E 0x80 /* set 2 enable */
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#define KA420_CADR_S1E 0x40 /* set 1 enable */
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#define KA420_CADR_ISE 0x20 /* insn caching enable */
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#define KA420_CADR_DSE 0x10 /* data caching enable */
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#define KA420_CADR_WWP 0x02 /* write wrong parity */
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#define KA420_CADR_DIA 0x01 /* diagnostic mode */
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/* Secondary cache bits (CACR, 20084000) */
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#define KA420_CACR_CP3 0x80000000 /* last parity read */
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#define KA420_CACR_CP2 0x40000000 /* last parity read */
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#define KA420_CACR_CP1 0x20000000 /* last parity read */
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#define KA420_CACR_CP0 0x10000000 /* last parity read */
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#define KA420_CACR_TPP 0x00100000 /* tag predicted parity */
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#define KA420_CACR_TGP 0x00080000 /* tag parity read */
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#define KA420_CACR_TGV 0x00040000 /* valid flag */
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#define KA420_CACR_TPE 0x00000020 /* tag parity error */
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#define KA420_CACR_CEN 0x00000010 /* cache enable */
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