874 lines
20 KiB
C
874 lines
20 KiB
C
/* Subroutines for assembler code output on the NS32000.
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Copyright (C) 1988, 1994, 1995 Free Software Foundation, Inc.
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This file is part of GNU CC.
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GNU CC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GNU CC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GNU CC; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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/* Some output-actions in ns32k.md need these. */
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#include <stdio.h>
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#include "config.h"
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#include "rtl.h"
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#include "regs.h"
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#include "hard-reg-set.h"
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#include "real.h"
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#include "insn-config.h"
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#include "conditions.h"
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#include "insn-flags.h"
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#include "output.h"
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#include "insn-attr.h"
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#ifdef OSF_OS
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int ns32k_num_files = 0;
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#endif
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void
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trace (s, s1, s2)
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char *s, *s1, *s2;
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{
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fprintf (stderr, s, s1, s2);
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}
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/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */
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int
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hard_regno_mode_ok (regno, mode)
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int regno;
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enum machine_mode mode;
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{
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switch (mode)
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{
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case QImode:
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case HImode:
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case PSImode:
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case SImode:
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case PDImode:
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case VOIDmode:
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case BLKmode:
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if (regno < 8 || regno == 16 || regno == 17)
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return 1;
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else
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return 0;
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case DImode:
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if (regno < 8 && (regno & 1) == 0)
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return 1;
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else
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return 0;
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case SFmode:
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case SCmode:
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if (TARGET_32081)
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{
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if (regno < 16)
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return 1;
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else
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return 0;
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}
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else
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{
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if (regno < 8)
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return 1;
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else
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return 0;
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}
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case DFmode:
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case DCmode:
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if ((regno & 1) == 0)
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{
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if (TARGET_32081)
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{
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if (regno < 16)
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return 1;
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else
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return 0;
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}
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else
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{
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if (regno < 8)
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return 1;
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else
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return 0;
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}
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}
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else
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return 0;
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}
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/* Used to abort here, but simply saying "no" handles TImode
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much better. */
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return 0;
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}
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/* ADDRESS_COST calls this. This function is not optimal
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for the 32032 & 32332, but it probably is better than
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the default. */
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int
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calc_address_cost (operand)
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rtx operand;
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{
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int i;
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int cost = 0;
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if (GET_CODE (operand) == MEM)
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cost += 3;
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if (GET_CODE (operand) == MULT)
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cost += 2;
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#if 0
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if (GET_CODE (operand) == REG)
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cost += 1; /* not really, but the documentation
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says different amount of registers
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shouldn't return the same costs */
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#endif
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switch (GET_CODE (operand))
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{
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case REG:
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case CONST:
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case CONST_INT:
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case CONST_DOUBLE:
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case SYMBOL_REF:
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case LABEL_REF:
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case POST_DEC:
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case PRE_DEC:
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break;
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case MULT:
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case MEM:
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case PLUS:
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for (i = 0; i < GET_RTX_LENGTH (GET_CODE (operand)); i++)
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{
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cost += calc_address_cost (XEXP (operand, i));
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}
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default:
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break;
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}
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return cost;
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}
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/* Return the register class of a scratch register needed to copy IN into
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or out of a register in CLASS in MODE. If it can be done directly,
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NO_REGS is returned. */
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enum reg_class
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secondary_reload_class (class, mode, in)
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enum reg_class class;
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enum machine_mode mode;
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rtx in;
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{
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int regno = true_regnum (in);
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if (regno >= FIRST_PSEUDO_REGISTER)
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regno = -1;
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/* We can place anything into GENERAL_REGS and can put GENERAL_REGS
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into anything. */
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if (class == GENERAL_REGS || (regno >= 0 && regno < 8))
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return NO_REGS;
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/* Constants, memory, and FP registers can go into FP registers. */
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if ((regno == -1 || (regno >= 8 && regno < 16)) && (class == FLOAT_REGS))
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return NO_REGS;
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#if 0 /* This isn't strictly true (can't move fp to sp or vice versa),
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so it's cleaner to use PREFERRED_RELOAD_CLASS
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to make the right things happen. */
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if (regno >= 16 && class == GEN_AND_MEM_REGS)
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return NO_REGS;
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#endif
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/* Otherwise, we need GENERAL_REGS. */
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return GENERAL_REGS;
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}
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/* Generate the rtx that comes from an address expression in the md file */
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/* The expression to be build is BASE[INDEX:SCALE]. To recognize this,
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scale must be converted from an exponent (from ASHIFT) to a
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multiplier (for MULT). */
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rtx
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gen_indexed_expr (base, index, scale)
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rtx base, index, scale;
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{
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rtx addr;
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/* This generates an invalid addressing mode, if BASE is
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fp or sp. This is handled by PRINT_OPERAND_ADDRESS. */
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if (GET_CODE (base) != REG && GET_CODE (base) != CONST_INT)
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base = gen_rtx (MEM, SImode, base);
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addr = gen_rtx (MULT, SImode, index,
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gen_rtx (CONST_INT, VOIDmode, 1 << INTVAL (scale)));
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addr = gen_rtx (PLUS, SImode, base, addr);
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return addr;
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}
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/* Return 1 if OP is a valid operand of mode MODE. This
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predicate rejects operands which do not have a mode
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(such as CONST_INT which are VOIDmode). */
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int
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reg_or_mem_operand (op, mode)
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register rtx op;
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enum machine_mode mode;
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{
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return (GET_MODE (op) == mode
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&& (GET_CODE (op) == REG
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|| GET_CODE (op) == SUBREG
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|| GET_CODE (op) == MEM));
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}
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/* Return the best assembler insn template
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for moving operands[1] into operands[0] as a fullword. */
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static char *
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singlemove_string (operands)
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rtx *operands;
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{
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if (GET_CODE (operands[1]) == CONST_INT
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&& INTVAL (operands[1]) <= 7
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&& INTVAL (operands[1]) >= -8)
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return "movqd %1,%0";
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return "movd %1,%0";
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}
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char *
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output_move_double (operands)
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rtx *operands;
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{
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enum anon1 { REGOP, OFFSOP, PUSHOP, CNSTOP, RNDOP } optype0, optype1;
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rtx latehalf[2];
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/* First classify both operands. */
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if (REG_P (operands[0]))
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optype0 = REGOP;
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else if (offsettable_memref_p (operands[0]))
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optype0 = OFFSOP;
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else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
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optype0 = PUSHOP;
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else
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optype0 = RNDOP;
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if (REG_P (operands[1]))
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optype1 = REGOP;
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else if (CONSTANT_P (operands[1])
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|| GET_CODE (operands[1]) == CONST_DOUBLE)
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optype1 = CNSTOP;
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else if (offsettable_memref_p (operands[1]))
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optype1 = OFFSOP;
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else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
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optype1 = PUSHOP;
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else
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optype1 = RNDOP;
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/* Check for the cases that the operand constraints are not
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supposed to allow to happen. Abort if we get one,
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because generating code for these cases is painful. */
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if (optype0 == RNDOP || optype1 == RNDOP)
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abort ();
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/* Ok, we can do one word at a time.
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Normally we do the low-numbered word first,
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but if either operand is autodecrementing then we
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do the high-numbered word first.
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In either case, set up in LATEHALF the operands to use
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for the high-numbered word and in some cases alter the
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operands in OPERANDS to be suitable for the low-numbered word. */
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if (optype0 == REGOP)
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latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
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else if (optype0 == OFFSOP)
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latehalf[0] = adj_offsettable_operand (operands[0], 4);
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else
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latehalf[0] = operands[0];
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if (optype1 == REGOP)
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latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
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else if (optype1 == OFFSOP)
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latehalf[1] = adj_offsettable_operand (operands[1], 4);
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else if (optype1 == CNSTOP)
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split_double (operands[1], &operands[1], &latehalf[1]);
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else
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latehalf[1] = operands[1];
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/* If insn is effectively movd N(sp),tos then we will do the
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high word first. We should use the adjusted operand 1 (which is N+4(sp))
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for the low word as well, to compensate for the first decrement of sp.
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Given this, it doesn't matter which half we do "first". */
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if (optype0 == PUSHOP
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&& REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
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&& reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
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operands[1] = latehalf[1];
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/* If one or both operands autodecrementing,
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do the two words, high-numbered first. */
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else if (optype0 == PUSHOP || optype1 == PUSHOP)
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{
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output_asm_insn (singlemove_string (latehalf), latehalf);
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return singlemove_string (operands);
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}
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/* If the first move would clobber the source of the second one,
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do them in the other order. */
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/* Overlapping registers. */
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if (optype0 == REGOP && optype1 == REGOP
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&& REGNO (operands[0]) == REGNO (latehalf[1]))
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{
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/* Do that word. */
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output_asm_insn (singlemove_string (latehalf), latehalf);
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/* Do low-numbered word. */
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return singlemove_string (operands);
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}
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/* Loading into a register which overlaps a register used in the address. */
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else if (optype0 == REGOP && optype1 != REGOP
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&& reg_overlap_mentioned_p (operands[0], operands[1]))
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{
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if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))
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&& reg_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
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{
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/* If both halves of dest are used in the src memory address,
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load the destination address into the low reg (operands[0]).
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Then it works to load latehalf first. */
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rtx xops[2];
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xops[0] = XEXP (operands[1], 0);
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xops[1] = operands[0];
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output_asm_insn ("addr %a0,%1", xops);
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operands[1] = gen_rtx (MEM, DImode, operands[0]);
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latehalf[1] = adj_offsettable_operand (operands[1], 4);
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/* The first half has the overlap, Do the late half first. */
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output_asm_insn (singlemove_string (latehalf), latehalf);
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/* Then clobber. */
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return singlemove_string (operands);
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}
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if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)))
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{
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/* The first half has the overlap, Do the late half first. */
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output_asm_insn (singlemove_string (latehalf), latehalf);
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/* Then clobber. */
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return singlemove_string (operands);
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}
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}
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/* Normal case. Do the two words, low-numbered first. */
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output_asm_insn (singlemove_string (operands), operands);
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operands[0] = latehalf[0];
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operands[1] = latehalf[1];
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return singlemove_string (operands);
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}
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int
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check_reg (oper, reg)
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rtx oper;
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int reg;
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{
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register int i;
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if (oper == 0)
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return 0;
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switch (GET_CODE(oper))
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{
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case REG:
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return (REGNO(oper) == reg) ? 1 : 0;
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case MEM:
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return check_reg(XEXP(oper, 0), reg);
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case PLUS:
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case MULT:
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return check_reg(XEXP(oper, 0), reg) || check_reg(XEXP(oper, 1), reg);
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}
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return 0;
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}
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/* Returns 1 if OP contains a global symbol reference */
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int
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global_symbolic_reference_mentioned_p (op, f)
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rtx op;
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int f;
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{
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register char *fmt;
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register int i;
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if (GET_CODE (op) == SYMBOL_REF)
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{
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if (! SYMBOL_REF_FLAG (op))
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return 1;
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else
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return 0;
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}
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else if (f && GET_CODE (op) != CONST)
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return 0;
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fmt = GET_RTX_FORMAT (GET_CODE (op));
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for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
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{
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if (fmt[i] == 'E')
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{
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register int j;
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for (j = XVECLEN (op, i) - 1; j >= 0; j--)
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if (global_symbolic_reference_mentioned_p (XVECEXP (op, i, j), 0))
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return 1;
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}
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else if (fmt[i] == 'e'
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&& global_symbolic_reference_mentioned_p (XEXP (op, i), 0))
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return 1;
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}
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return 0;
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}
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/* PRINT_OPERAND is defined to call this function,
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which is easier to debug than putting all the code in
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a macro definition in ns32k.h. */
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void
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print_operand (file, x, code)
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FILE *file;
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rtx x;
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char code;
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{
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if (code == '$')
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PUT_IMMEDIATE_PREFIX (file);
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else if (code == '?')
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PUT_EXTERNAL_PREFIX (file);
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else if (GET_CODE (x) == REG)
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fprintf (file, "%s", reg_names[REGNO (x)]);
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else if (GET_CODE (x) == MEM)
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{
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rtx tmp = XEXP (x, 0);
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output_address (XEXP (x, 0));
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}
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else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode)
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{
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if (GET_MODE (x) == DFmode)
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{
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union { double d; int i[2]; } u;
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u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x);
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PUT_IMMEDIATE_PREFIX(file);
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#ifdef SEQUENT_ASM
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/* Sequent likes it's floating point constants as integers */
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fprintf (file, "0Dx%08x%08x", u.i[1], u.i[0]);
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#else
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#ifdef ENCORE_ASM
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fprintf (file, "0f%.20e", u.d);
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#else
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fprintf (file, "0d%.20e", u.d);
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#endif
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#endif
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}
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else
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{
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union { double d; int i[2]; } u;
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u.i[0] = CONST_DOUBLE_LOW (x); u.i[1] = CONST_DOUBLE_HIGH (x);
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PUT_IMMEDIATE_PREFIX (file);
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#ifdef SEQUENT_ASM
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/* We have no way of winning if we can't get the bits
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for a sequent floating point number. */
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#if HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
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abort ();
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#endif
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{
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union { float f; long l; } uu;
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uu.f = u.d;
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fprintf (file, "0Fx%08x", uu.l);
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}
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#else
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fprintf (file, "0f%.20e", u.d);
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#endif
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}
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}
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else
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{
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#ifdef NO_IMMEDIATE_PREFIX_IF_SYMBOLIC
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if (GET_CODE (x) == CONST_INT)
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#endif
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PUT_IMMEDIATE_PREFIX (file);
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output_addr_const (file, x);
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}
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}
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/* PRINT_OPERAND_ADDRESS is defined to call this function,
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which is easier to debug than putting all the code in
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a macro definition in ns32k.h . */
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/* Completely rewritten to get this to work with Gas for PC532 Mach.
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This function didn't work and I just wasn't able (nor very willing) to
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figure out how it worked.
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90-11-25 Tatu Yl|nen <ylo@cs.hut.fi> */
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print_operand_address (file, addr)
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register FILE *file;
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register rtx addr;
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{
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static char scales[] = { 'b', 'w', 'd', 0, 'q', };
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rtx offset, base, indexexp, tmp;
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int scale;
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extern int flag_pic;
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if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == POST_DEC)
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{
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||
fprintf (file, "tos");
|
||
return;
|
||
}
|
||
|
||
offset = NULL;
|
||
base = NULL;
|
||
indexexp = NULL;
|
||
while (addr != NULL)
|
||
{
|
||
if (GET_CODE (addr) == PLUS)
|
||
{
|
||
if (GET_CODE (XEXP (addr, 0)) == PLUS)
|
||
{
|
||
tmp = XEXP (addr, 1);
|
||
addr = XEXP (addr, 0);
|
||
}
|
||
else
|
||
{
|
||
tmp = XEXP (addr,0);
|
||
addr = XEXP (addr,1);
|
||
}
|
||
}
|
||
else
|
||
{
|
||
tmp = addr;
|
||
addr = NULL;
|
||
}
|
||
switch (GET_CODE (tmp))
|
||
{
|
||
case PLUS:
|
||
abort ();
|
||
case MEM:
|
||
if (base)
|
||
{
|
||
indexexp = base;
|
||
base = tmp;
|
||
}
|
||
else
|
||
base = tmp;
|
||
break;
|
||
case REG:
|
||
if (REGNO (tmp) < 8)
|
||
if (base)
|
||
{
|
||
indexexp = tmp;
|
||
}
|
||
else
|
||
base = tmp;
|
||
else
|
||
if (base)
|
||
{
|
||
indexexp = base;
|
||
base = tmp;
|
||
}
|
||
else
|
||
base = tmp;
|
||
break;
|
||
case MULT:
|
||
indexexp = tmp;
|
||
break;
|
||
case SYMBOL_REF:
|
||
if (flag_pic && ! CONSTANT_POOL_ADDRESS_P (tmp)
|
||
&& ! SYMBOL_REF_FLAG (tmp))
|
||
{
|
||
if (base)
|
||
{
|
||
if (indexexp)
|
||
abort ();
|
||
indexexp = base;
|
||
}
|
||
base = tmp;
|
||
break;
|
||
}
|
||
case CONST:
|
||
if (flag_pic && GET_CODE (tmp) == CONST)
|
||
{
|
||
rtx sym, off, tmp1;
|
||
tmp1 = XEXP (tmp,0);
|
||
if (GET_CODE (tmp1) != PLUS)
|
||
abort ();
|
||
|
||
sym = XEXP (tmp1,0);
|
||
if (GET_CODE (sym) != SYMBOL_REF)
|
||
{
|
||
off = sym;
|
||
sym = XEXP (tmp1,1);
|
||
}
|
||
else
|
||
off = XEXP (tmp1,1);
|
||
if (GET_CODE (sym) == SYMBOL_REF)
|
||
{
|
||
if (GET_CODE (off) != CONST_INT)
|
||
abort ();
|
||
|
||
if (CONSTANT_POOL_ADDRESS_P (sym)
|
||
|| SYMBOL_REF_FLAG (sym))
|
||
{
|
||
SYMBOL_REF_FLAG (tmp) = 1;
|
||
}
|
||
else
|
||
{
|
||
if (base)
|
||
{
|
||
if (indexexp)
|
||
abort ();
|
||
|
||
indexexp = base;
|
||
}
|
||
|
||
if (offset != 0)
|
||
abort ();
|
||
|
||
base = sym;
|
||
offset = off;
|
||
break;
|
||
}
|
||
}
|
||
}
|
||
case CONST_INT:
|
||
case LABEL_REF:
|
||
if (offset)
|
||
offset = gen_rtx (PLUS, SImode, tmp, offset);
|
||
else
|
||
offset = tmp;
|
||
break;
|
||
default:
|
||
abort ();
|
||
}
|
||
}
|
||
if (! offset)
|
||
offset = const0_rtx;
|
||
|
||
if (base
|
||
#ifndef INDEX_RATHER_THAN_BASE
|
||
&& (flag_pic || TARGET_HIMEM)
|
||
&& GET_CODE (base) != SYMBOL_REF
|
||
&& GET_CODE (offset) != CONST_INT
|
||
#else
|
||
/* This is a re-implementation of the SEQUENT_ADDRESS_BUG fix. */
|
||
#endif
|
||
&& !indexexp && GET_CODE (base) == REG
|
||
&& REG_OK_FOR_INDEX_P (base))
|
||
{
|
||
indexexp = base;
|
||
base = NULL;
|
||
}
|
||
|
||
/* now, offset, base and indexexp are set */
|
||
#ifndef BASE_REG_NEEDED
|
||
if (! base)
|
||
{
|
||
#if defined (PC_RELATIVE) || defined (NO_ABSOLUTE_PREFIX_IF_SYMBOLIC)
|
||
if (GET_CODE (offset) == CONST_INT)
|
||
#endif
|
||
PUT_ABSOLUTE_PREFIX (file);
|
||
}
|
||
#endif
|
||
|
||
output_addr_const (file, offset);
|
||
if (base) /* base can be (REG ...) or (MEM ...) */
|
||
switch (GET_CODE (base))
|
||
{
|
||
/* now we must output base. Possible alternatives are:
|
||
(rN) (REG ...)
|
||
(sp) (REG ...)
|
||
(fp) (REG ...)
|
||
(pc) (REG ...) used for SYMBOL_REF and LABEL_REF, output
|
||
(disp(fp)) (MEM ...) just before possible [rX:y]
|
||
(disp(sp)) (MEM ...)
|
||
(disp(sb)) (MEM ...)
|
||
*/
|
||
case REG:
|
||
fprintf (file, "(%s)", reg_names[REGNO (base)]);
|
||
break;
|
||
case SYMBOL_REF:
|
||
if (! flag_pic)
|
||
abort ();
|
||
|
||
fprintf (file, "(");
|
||
output_addr_const (file, base);
|
||
fprintf (file, "(sb))");
|
||
break;
|
||
case MEM:
|
||
addr = XEXP(base,0);
|
||
base = NULL;
|
||
offset = NULL;
|
||
while (addr != NULL)
|
||
{
|
||
if (GET_CODE (addr) == PLUS)
|
||
{
|
||
if (GET_CODE (XEXP (addr, 0)) == PLUS)
|
||
{
|
||
tmp = XEXP (addr, 1);
|
||
addr = XEXP (addr, 0);
|
||
}
|
||
else
|
||
{
|
||
tmp = XEXP (addr, 0);
|
||
addr = XEXP (addr, 1);
|
||
}
|
||
}
|
||
else
|
||
{
|
||
tmp = addr;
|
||
addr = NULL;
|
||
}
|
||
switch (GET_CODE (tmp))
|
||
{
|
||
case REG:
|
||
base = tmp;
|
||
break;
|
||
case CONST:
|
||
case CONST_INT:
|
||
case SYMBOL_REF:
|
||
case LABEL_REF:
|
||
if (offset)
|
||
offset = gen_rtx (PLUS, SImode, tmp, offset);
|
||
else
|
||
offset = tmp;
|
||
break;
|
||
default:
|
||
abort ();
|
||
}
|
||
}
|
||
if (! offset)
|
||
offset = const0_rtx;
|
||
fprintf (file, "(");
|
||
output_addr_const (file, offset);
|
||
if (base)
|
||
fprintf (file, "(%s)", reg_names[REGNO (base)]);
|
||
else if (TARGET_SB)
|
||
fprintf (file, "(sb)");
|
||
else
|
||
abort ();
|
||
fprintf (file, ")");
|
||
break;
|
||
default:
|
||
abort ();
|
||
}
|
||
#ifdef PC_RELATIVE
|
||
else if (GET_CODE (offset) != CONST_INT)
|
||
fprintf (file, "(pc)");
|
||
#ifdef BASE_REG_NEEDED
|
||
else if (TARGET_SB)
|
||
fprintf (file, "(sb)");
|
||
else
|
||
abort ();
|
||
#endif
|
||
#endif /* PC_RELATIVE */
|
||
|
||
/* now print index if we have one */
|
||
if (indexexp)
|
||
{
|
||
if (GET_CODE (indexexp) == MULT)
|
||
{
|
||
scale = INTVAL (XEXP (indexexp, 1)) >> 1;
|
||
indexexp = XEXP (indexexp, 0);
|
||
}
|
||
else
|
||
scale = 0;
|
||
if (GET_CODE (indexexp) != REG || REGNO (indexexp) >= 8)
|
||
abort ();
|
||
|
||
#ifdef UTEK_ASM
|
||
fprintf (file, "[%c`%s]",
|
||
scales[scale],
|
||
reg_names[REGNO (indexexp)]);
|
||
#else
|
||
fprintf (file, "[%s:%c]",
|
||
reg_names[REGNO (indexexp)],
|
||
scales[scale]);
|
||
#endif
|
||
}
|
||
}
|
||
|
||
/* National 32032 shifting is so bad that we can get
|
||
better performance in many common cases by using other
|
||
techniques. */
|
||
char *
|
||
output_shift_insn (operands)
|
||
rtx *operands;
|
||
{
|
||
if (GET_CODE (operands[2]) == CONST_INT
|
||
&& INTVAL (operands[2]) > 0
|
||
&& INTVAL (operands[2]) <= 3)
|
||
if (GET_CODE (operands[0]) == REG)
|
||
{
|
||
if (GET_CODE (operands[1]) == REG)
|
||
{
|
||
if (REGNO (operands[0]) == REGNO (operands[1]))
|
||
{
|
||
if (operands[2] == const1_rtx)
|
||
return "addd %0,%0";
|
||
else if (INTVAL (operands[2]) == 2)
|
||
return "addd %0,%0\n\taddd %0,%0";
|
||
}
|
||
if (operands[2] == const1_rtx)
|
||
return "movd %1,%0\n\taddd %0,%0";
|
||
|
||
operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
|
||
return "addr %a1,%0";
|
||
}
|
||
if (operands[2] == const1_rtx)
|
||
return "movd %1,%0\n\taddd %0,%0";
|
||
}
|
||
else if (GET_CODE (operands[1]) == REG)
|
||
{
|
||
operands[1] = gen_indexed_expr (const0_rtx, operands[1], operands[2]);
|
||
return "addr %a1,%0";
|
||
}
|
||
else if (INTVAL (operands[2]) == 1
|
||
&& GET_CODE (operands[1]) == MEM
|
||
&& rtx_equal_p (operands [0], operands[1]))
|
||
{
|
||
rtx temp = XEXP (operands[1], 0);
|
||
|
||
if (GET_CODE (temp) == REG
|
||
|| (GET_CODE (temp) == PLUS
|
||
&& GET_CODE (XEXP (temp, 0)) == REG
|
||
&& GET_CODE (XEXP (temp, 1)) == CONST_INT))
|
||
return "addd %0,%0";
|
||
}
|
||
else return "ashd %2,%0";
|
||
return "ashd %2,%0";
|
||
}
|
||
|
||
char *
|
||
output_move_dconst (n, s)
|
||
int n;
|
||
char *s;
|
||
{
|
||
static char r[32];
|
||
|
||
if (n > -9 && n < 8)
|
||
strcpy (r, "movqd ");
|
||
else if (n > 0 && n < 256)
|
||
strcpy (r, "movzbd ");
|
||
else if (n > 0 && n < 65536)
|
||
strcpy (r, "movzwd ");
|
||
else if (n < 0 && n > -129)
|
||
strcpy (r, "movxbd ");
|
||
else if (n < 0 && n > -32769)
|
||
strcpy (r, "movxwd ");
|
||
else
|
||
strcpy (r, "movd ");
|
||
strcat (r, s);
|
||
return r;
|
||
}
|