139 lines
5.5 KiB
C
139 lines
5.5 KiB
C
/* $NetBSD: miidevs.h,v 1.6 1999/05/14 11:38:05 drochner Exp $ */
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/*
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* THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
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*
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* generated from:
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* NetBSD: miidevs,v 1.6 1999/05/14 11:37:30 drochner Exp
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*/
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/*-
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* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* List of known MII OUIs.
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* For a complete list see http://standards.ieee.org/regauth/oui/
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*
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* XXX Vendors do obviously not agree how OUIs (18 bit) are mapped
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* to the 16 bits available in the id registers. The MII_OUI() macro
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* in "mii.h" reflects the most obvious way. If a vendor uses a
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* different mapping, an "xx" prefixed OUI is defined here which is
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* mangled accordingly to compensate.
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*/
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#define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */
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#define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */
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#define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */
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#define MII_OUI_INTEL 0x00aa00 /* Intel */
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#define MII_OUI_LEVEL1 0x00207b /* Level 1 */
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#define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */
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#define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */
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#define MII_OUI_SEEQ 0x00a07d /* Seeq */
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#define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */
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#define MII_OUI_TI 0x080028 /* Texas Instruments */
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/* in the 79c873, AMD uses another OUI (which matches Davicom!) */
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#define MII_OUI_xxAMD 0x00606e /* Advanced Micro Devices */
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/* some vendors have the bits swapped within bytes
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(ie, ordered as on the wire) */
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#define MII_OUI_xxICS 0x00057d /* Integrated Circuit Systems */
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#define MII_OUI_xxSEEQ 0x0005be /* Seeq */
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#define MII_OUI_xxSIS 0x000760 /* Silicon Integrated Systems */
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#define MII_OUI_xxTI 0x100014 /* Texas Instruments */
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/* Level 1 is completely different - from right to left.
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(Two bits get lost in the third OUI byte.) */
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#define MII_OUI_xxLEVEL1 0x1e0400 /* Level 1 */
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/* Don't know what's going on here. */
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#define MII_OUI_xxDAVICOM 0x006040 /* Davicom Semiconductor */
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/*
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* List of known models. Grouped by oui.
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*/
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/* Advanced Micro Devices PHYs */
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#define MII_MODEL_xxAMD_79C873 0x0000
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#define MII_STR_xxAMD_79C873 "Am79C873 10/100 media interface"
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#define MII_MODEL_AMD_79c973phy 0x0036
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#define MII_STR_AMD_79c973phy "Am79c973 internal PHY"
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/* Davicom Semiconductor PHYs */
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#define MII_MODEL_xxDAVICOM_DM9101 0x0000
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#define MII_STR_xxDAVICOM_DM9101 "DM9101 10/100 media interface"
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/* Integrated Circuit Systems PHYs */
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#define MII_MODEL_xxICS_1890 0x0002
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#define MII_STR_xxICS_1890 "ICS1890 10/100 media interface"
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/* Intel PHYs */
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#define MII_MODEL_INTEL_I82555 0x0015
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#define MII_STR_INTEL_I82555 "i82555 10/100 media interface"
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/* Level 1 PHYs */
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#define MII_MODEL_xxLEVEL1_LXT970 0x0000
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#define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface"
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/* National Semiconductor PHYs */
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#define MII_MODEL_NATSEMI_DP83840 0x0000
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#define MII_STR_NATSEMI_DP83840 "DP83840 10/100 media interface"
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#define MII_MODEL_NATSEMI_DP83843 0x0001
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#define MII_STR_NATSEMI_DP83843 "DP83843 10/100 media interface"
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/* Quality Semiconductor PHYs */
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#define MII_MODEL_QUALSEMI_QS6612 0x0000
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#define MII_STR_QUALSEMI_QS6612 "QS6612 10/100 media interface"
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/* Seeq PHYs */
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#define MII_MODEL_xxSEEQ_80220 0x0003
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#define MII_STR_xxSEEQ_80220 "Seeq 80220 10/100 media interface"
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#define MII_MODEL_xxSEEQ_84220 0x0004
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#define MII_STR_xxSEEQ_84220 "Seeq 84220 10/100 media interface"
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/* Silicon Integrated Systems PHYs */
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#define MII_MODEL_xxSIS_900 0x0000
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#define MII_STR_xxSIS_900 "SiS 900 10/100 media interface"
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/* Texas Instruments PHYs */
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#define MII_MODEL_xxTI_TLAN10T 0x0001
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#define MII_STR_xxTI_TLAN10T "ThunderLAN 10baseT media interface"
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#define MII_MODEL_xxTI_100VGPMI 0x0002
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#define MII_STR_xxTI_100VGPMI "ThunderLAN 100VG-AnyLan media interface"
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