1583 lines
41 KiB
C
1583 lines
41 KiB
C
/* $NetBSD: unichromefb.c,v 1.7 2007/03/23 22:17:30 jmcneill Exp $ */
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/*-
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* Copyright (c) 2006 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Jared D. McNeill.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright 1998-2006 VIA Technologies, Inc. All Rights Reserved.
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* Copyright 2001-2006 S3 Graphics, Inc. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sub license,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: unichromefb.c,v 1.7 2007/03/23 22:17:30 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <machine/bus.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/wscons/wsdisplayvar.h>
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#include <dev/wscons/wsconsio.h>
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#include <dev/wsfont/wsfont.h>
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#include <dev/rasops/rasops.h>
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#include <dev/wscons/wsdisplay_vconsvar.h>
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#include <dev/pci/unichromereg.h>
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#include <dev/pci/unichromemode.h>
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#include <dev/pci/unichromehw.h>
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#include <dev/pci/unichromeconfig.h>
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#include <dev/pci/unichromeaccel.h>
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#include "vga.h"
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#if NVGA > 0
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#include <dev/ic/mc6845reg.h>
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#include <dev/ic/pcdisplayvar.h>
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#include <dev/ic/vgareg.h>
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#include <dev/ic/vgavar.h>
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#endif
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/* XXX */
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#define UNICHROMEFB_DEPTH 16
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#define UNICHROMEFB_MODE VIA_RES_1280X1024
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#define UNICHROMEFB_WIDTH 1280
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#define UNICHROMEFB_HEIGHT 1024
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struct unichromefb_softc {
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struct device sc_dev;
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struct vcons_data sc_vd;
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void * sc_fbbase;
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unsigned int sc_fbaddr;
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unsigned int sc_fbsize;
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bus_addr_t sc_mmiobase;
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bus_size_t sc_mmiosize;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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bus_space_tag_t sc_memt;
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bus_space_handle_t sc_memh;
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bus_space_handle_t sc_apmemt;
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bus_space_handle_t sc_apmemh;
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struct pci_attach_args sc_pa;
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int sc_width;
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int sc_height;
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int sc_depth;
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int sc_stride;
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int sc_wsmode;
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int sc_accel;
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};
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static int unichromefb_match(struct device *, struct cfdata *, void *);
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static void unichromefb_attach(struct device *, struct device *, void *);
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static int unichromefb_drm_print(void *, const char *);
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static int unichromefb_drm_unmap(struct unichromefb_softc *);
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static int unichromefb_drm_map(struct unichromefb_softc *);
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struct wsscreen_descr unichromefb_stdscreen = {
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"fb",
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0, 0,
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NULL,
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8, 16,
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WSSCREEN_WSCOLORS, NULL,
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};
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static int unichromefb_ioctl(void *, void *, u_long, void *, int,
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struct lwp *);
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static paddr_t unichromefb_mmap(void *, void *, off_t, int);
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static void unichromefb_init_screen(void *, struct vcons_screen *,
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int, long *);
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/* hardware access */
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static uint8_t uni_rd(struct unichromefb_softc *, int, uint8_t);
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static void uni_wr(struct unichromefb_softc *, int, uint8_t, uint8_t);
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static void uni_wr_mask(struct unichromefb_softc *, int, uint8_t,
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uint8_t, uint8_t);
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static void uni_wr_x(struct unichromefb_softc *, struct io_reg *, int);
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static void uni_wr_dac(struct unichromefb_softc *, uint8_t, uint8_t,
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uint8_t, uint8_t);
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/* helpers */
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static struct VideoModeTable * uni_getmode(int);
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static void uni_setmode(struct unichromefb_softc *, int, int);
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static void uni_crt_lock(struct unichromefb_softc *);
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static void uni_crt_unlock(struct unichromefb_softc *);
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static void uni_crt_enable(struct unichromefb_softc *);
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static void uni_crt_disable(struct unichromefb_softc *);
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static void uni_screen_enable(struct unichromefb_softc *);
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static void uni_screen_disable(struct unichromefb_softc *);
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static void uni_set_start(struct unichromefb_softc *);
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static void uni_set_crtc(struct unichromefb_softc *,
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struct crt_mode_table *, int, int, int);
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static void uni_load_crtc(struct unichromefb_softc *, struct display_timing,
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int);
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static void uni_load_reg(struct unichromefb_softc *, int, int,
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struct io_register *, int);
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static void uni_fix_crtc(struct unichromefb_softc *);
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static void uni_load_offset(struct unichromefb_softc *, int, int, int);
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static void uni_load_fetchcnt(struct unichromefb_softc *, int, int, int);
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static void uni_load_fifo(struct unichromefb_softc *, int, int, int);
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static void uni_set_depth(struct unichromefb_softc *, int, int);
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static uint32_t uni_get_clkval(struct unichromefb_softc *, int);
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static void uni_set_vclk(struct unichromefb_softc *, uint32_t, int);
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static void uni_init_dac(struct unichromefb_softc *, int);
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static void uni_init_accel(struct unichromefb_softc *);
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static void uni_set_accel_depth(struct unichromefb_softc *);
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/* graphics ops */
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static void uni_wait_idle(struct unichromefb_softc *);
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static void uni_fillrect(struct unichromefb_softc *,
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int, int, int, int, int);
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static void uni_rectinvert(struct unichromefb_softc *,
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int, int, int, int);
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static void uni_bitblit(struct unichromefb_softc *, int, int, int, int,
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int, int);
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static void uni_setup_mono(struct unichromefb_softc *, int, int, int,
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int, uint32_t, uint32_t);
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#if notyet
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static void uni_cursor_show(struct unichromefb_softc *);
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static void uni_cursor_hide(struct unichromefb_softc *);
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#endif
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/* rasops glue */
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static void uni_copycols(void *, int, int, int, int);
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static void uni_copyrows(void *, int, int, int);
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static void uni_erasecols(void *, int, int, int, long);
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static void uni_eraserows(void *, int, int, long);
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static void uni_cursor(void *, int, int, int);
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static void uni_putchar(void *, int, int, u_int, long);
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struct wsdisplay_accessops unichromefb_accessops = {
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unichromefb_ioctl,
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unichromefb_mmap,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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};
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static struct vcons_screen unichromefb_console_screen;
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const struct wsscreen_descr *_unichromefb_scrlist[] = {
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&unichromefb_stdscreen,
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};
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struct wsscreen_list unichromefb_screenlist = {
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sizeof(_unichromefb_scrlist) / sizeof(struct wsscreen_descr *),
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_unichromefb_scrlist
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};
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CFATTACH_DECL(unichromefb, sizeof(struct unichromefb_softc),
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unichromefb_match, unichromefb_attach, NULL, NULL);
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static int
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unichromefb_match(struct device *parent, struct cfdata *match, void *opaque)
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{
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struct pci_attach_args *pa;
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pa = (struct pci_attach_args *)opaque;
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if (PCI_CLASS(pa->pa_class) != PCI_CLASS_DISPLAY ||
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PCI_SUBCLASS(pa->pa_class) != PCI_SUBCLASS_DISPLAY_VGA)
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return 0;
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if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_VIATECH)
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return 0;
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switch (PCI_PRODUCT(pa->pa_id)) {
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case PCI_PRODUCT_VIATECH_VT3314_IG:
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return 10; /* beat vga(4) */
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}
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return 0;
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}
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static void
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unichromefb_attach(struct device *parent, struct device *self, void *opaque)
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{
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struct unichromefb_softc *sc;
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struct pci_attach_args *pa;
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struct rasops_info *ri;
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struct wsemuldisplaydev_attach_args aa;
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uint8_t val;
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long defattr;
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sc = (struct unichromefb_softc *)self;
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pa = (struct pci_attach_args *)opaque;
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sc->sc_width = UNICHROMEFB_WIDTH;
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sc->sc_height = UNICHROMEFB_HEIGHT;
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sc->sc_depth = UNICHROMEFB_DEPTH;
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sc->sc_stride = sc->sc_width * (sc->sc_depth / 8);
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sc->sc_wsmode = WSDISPLAYIO_MODE_EMUL;
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sc->sc_iot = pa->pa_iot;
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sc->sc_pa = *pa;
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#if NVGA > 0
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/* XXX vga_cnattach claims the I/O registers that we need;
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* we need to nuke it here so we can take over.
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*/
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vga_cndetach();
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#endif
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if (bus_space_map(sc->sc_iot, VIA_REGBASE, 0x20, 0, &sc->sc_ioh)) {
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aprint_error(": failed to map I/O registers\n");
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return;
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}
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sc->sc_apmemt = pa->pa_memt;
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val = uni_rd(sc, VIASR, SR30);
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sc->sc_fbaddr = val << 24;
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val = uni_rd(sc, VIASR, SR39);
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sc->sc_fbsize = val * (4*1024*1024);
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if (sc->sc_fbsize < 16*1024*1024 || sc->sc_fbsize > 64*1024*1024)
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sc->sc_fbsize = 16*1024*1024;
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if (bus_space_map(sc->sc_apmemt, sc->sc_fbaddr, sc->sc_fbsize,
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BUS_SPACE_MAP_LINEAR, &sc->sc_apmemh)) {
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aprint_error(": failed to map aperture at 0x%08x/0x%x\n",
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sc->sc_fbaddr, sc->sc_fbsize);
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return;
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}
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sc->sc_fbbase = (void *)bus_space_vaddr(sc->sc_apmemt, sc->sc_apmemh);
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if (pci_mapreg_map(pa, 0x14, PCI_MAPREG_TYPE_MEM, 0,
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&sc->sc_memt, &sc->sc_memh, &sc->sc_mmiobase,
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&sc->sc_mmiosize)) {
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sc->sc_accel = 0;
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aprint_error(": failed to map MMIO registers\n");
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} else {
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sc->sc_accel = 1;
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}
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aprint_naive("\n");
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aprint_normal(": VIA UniChrome frame buffer\n");
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if (sc->sc_accel)
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aprint_normal("%s: MMIO @0x%08x/0x%x\n",
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sc->sc_dev.dv_xname,
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(uint32_t)sc->sc_mmiobase,
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(uint32_t)sc->sc_mmiosize);
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ri = &unichromefb_console_screen.scr_ri;
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memset(ri, 0, sizeof(struct rasops_info));
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vcons_init(&sc->sc_vd, sc, &unichromefb_stdscreen,
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&unichromefb_accessops);
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sc->sc_vd.init_screen = unichromefb_init_screen;
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uni_setmode(sc, UNICHROMEFB_MODE, sc->sc_depth);
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uni_init_dac(sc, IGA1);
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if (sc->sc_accel) {
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uni_init_accel(sc);
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uni_fillrect(sc, 0, 0, sc->sc_width, sc->sc_height, 0);
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}
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aprint_normal("%s: FB @0x%08x (%dx%dx%d)\n", sc->sc_dev.dv_xname,
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sc->sc_fbaddr, sc->sc_width, sc->sc_height, sc->sc_depth);
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unichromefb_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC;
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vcons_init_screen(&sc->sc_vd, &unichromefb_console_screen, 1, &defattr);
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unichromefb_stdscreen.ncols = ri->ri_cols;
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unichromefb_stdscreen.nrows = ri->ri_rows;
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unichromefb_stdscreen.textops = &ri->ri_ops;
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unichromefb_stdscreen.capabilities = ri->ri_caps;
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unichromefb_stdscreen.modecookie = NULL;
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wsdisplay_cnattach(&unichromefb_stdscreen, ri, 0, 0, defattr);
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aa.console = 1; /* XXX */
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aa.scrdata = &unichromefb_screenlist;
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aa.accessops = &unichromefb_accessops;
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aa.accesscookie = &sc->sc_vd;
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config_found(self, &aa, wsemuldisplaydevprint);
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config_found_ia(self, "drm", opaque, unichromefb_drm_print);
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return;
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}
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static int
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unichromefb_drm_print(void *opaque, const char *pnp)
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{
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if (pnp)
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aprint_normal("direct rendering for %s", pnp);
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return UNSUPP;
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}
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static int
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unichromefb_drm_unmap(struct unichromefb_softc *sc)
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{
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printf("%s: releasing bus resources\n", sc->sc_dev.dv_xname);
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bus_space_unmap(sc->sc_apmemt, sc->sc_apmemh, sc->sc_fbsize);
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bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_mmiosize);
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bus_space_unmap(sc->sc_iot, sc->sc_ioh, 0x20);
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return 0;
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}
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static int
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unichromefb_drm_map(struct unichromefb_softc *sc)
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{
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int rv;
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rv = bus_space_map(sc->sc_iot, VIA_REGBASE, 0x20, 0,
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&sc->sc_ioh);
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if (rv) {
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printf("%s: failed to map I/O registers\n",
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sc->sc_dev.dv_xname);
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return rv;
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}
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rv = bus_space_map(sc->sc_apmemt, sc->sc_fbaddr, sc->sc_fbsize,
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BUS_SPACE_MAP_LINEAR, &sc->sc_apmemh);
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if (rv) {
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printf("%s: failed to map aperture at 0x%08x/0x%x\n",
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sc->sc_dev.dv_xname, sc->sc_fbaddr, sc->sc_fbsize);
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return rv;
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}
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sc->sc_fbbase = (void *)bus_space_vaddr(sc->sc_apmemt, sc->sc_apmemh);
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rv = pci_mapreg_map(&sc->sc_pa, 0x14, PCI_MAPREG_TYPE_MEM, 0,
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&sc->sc_memt, &sc->sc_memh, &sc->sc_mmiobase,
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&sc->sc_mmiosize);
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if (rv) {
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printf("%s: failed to map MMIO registers\n",
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sc->sc_dev.dv_xname);
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sc->sc_accel = 0;
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}
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uni_setmode(sc, UNICHROMEFB_MODE, sc->sc_depth);
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uni_init_dac(sc, IGA1);
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if (sc->sc_accel) {
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uni_init_accel(sc);
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}
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printf("%s: re-acquired bus resources\n", sc->sc_dev.dv_xname);
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return 0;
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}
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static int
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unichromefb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag,
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struct lwp *l)
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{
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struct vcons_data *vd;
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struct unichromefb_softc *sc;
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struct wsdisplay_fbinfo *fb;
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vd = (struct vcons_data *)v;
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sc = (struct unichromefb_softc *)vd->cookie;
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switch (cmd) {
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case WSDISPLAYIO_GTYPE:
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*(u_int *)data = WSDISPLAY_TYPE_PCIMISC;
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return 0;
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case WSDISPLAYIO_GINFO:
|
|
if (vd->active != NULL) {
|
|
fb = (struct wsdisplay_fbinfo *)data;
|
|
fb->width = sc->sc_width;
|
|
fb->height = sc->sc_height;
|
|
fb->depth = sc->sc_depth;
|
|
fb->cmsize = 256;
|
|
return 0;
|
|
} else
|
|
return ENODEV;
|
|
case WSDISPLAYIO_GVIDEO:
|
|
return ENODEV;
|
|
case WSDISPLAYIO_SVIDEO:
|
|
return ENODEV;
|
|
case WSDISPLAYIO_GETCMAP:
|
|
return EINVAL;
|
|
case WSDISPLAYIO_PUTCMAP:
|
|
return EINVAL;
|
|
case WSDISPLAYIO_LINEBYTES:
|
|
*(u_int *)data = sc->sc_stride;
|
|
return 0;
|
|
case WSDISPLAYIO_SMODE:
|
|
{
|
|
int new_mode = *(int *)data;
|
|
if (new_mode != sc->sc_wsmode) {
|
|
sc->sc_wsmode = new_mode;
|
|
switch (new_mode) {
|
|
case WSDISPLAYIO_MODE_EMUL:
|
|
unichromefb_drm_map(sc);
|
|
vcons_redraw_screen(vd->active);
|
|
break;
|
|
default:
|
|
unichromefb_drm_unmap(sc);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
return 0;
|
|
case WSDISPLAYIO_SSPLASH:
|
|
return ENODEV;
|
|
case WSDISPLAYIO_SPROGRESS:
|
|
return ENODEV;
|
|
}
|
|
|
|
return EPASSTHROUGH;
|
|
}
|
|
|
|
static paddr_t
|
|
unichromefb_mmap(void *v, void *vs, off_t offset, int prot)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
static void
|
|
unichromefb_init_screen(void *c, struct vcons_screen *scr, int existing,
|
|
long *defattr)
|
|
{
|
|
struct unichromefb_softc *sc;
|
|
struct rasops_info *ri;
|
|
|
|
sc = (struct unichromefb_softc *)c;
|
|
ri = &scr->scr_ri;
|
|
ri->ri_flg = RI_CENTER;
|
|
ri->ri_depth = sc->sc_depth;
|
|
ri->ri_width = sc->sc_width;
|
|
ri->ri_height = sc->sc_height;
|
|
ri->ri_stride = sc->sc_stride;
|
|
ri->ri_bits = sc->sc_fbbase;
|
|
if (existing)
|
|
ri->ri_flg |= RI_CLEAR;
|
|
|
|
switch (ri->ri_depth) {
|
|
case 32:
|
|
ri->ri_rnum = ri->ri_gnum = ri->ri_bnum = 8;
|
|
ri->ri_rpos = 16;
|
|
ri->ri_gpos = 8;
|
|
ri->ri_bpos = 0;
|
|
break;
|
|
case 16:
|
|
ri->ri_rnum = 5;
|
|
ri->ri_gnum = 6;
|
|
ri->ri_bnum = 5;
|
|
ri->ri_rpos = 11;
|
|
ri->ri_gpos = 5;
|
|
ri->ri_bpos = 0;
|
|
break;
|
|
}
|
|
|
|
rasops_init(ri, sc->sc_height / 16, sc->sc_width / 8);
|
|
ri->ri_caps = WSSCREEN_WSCOLORS;
|
|
rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight,
|
|
sc->sc_width / ri->ri_font->fontwidth);
|
|
|
|
ri->ri_hw = scr;
|
|
if (sc->sc_accel) {
|
|
ri->ri_ops.copyrows = uni_copyrows;
|
|
ri->ri_ops.copycols = uni_copycols;
|
|
ri->ri_ops.eraserows = uni_eraserows;
|
|
ri->ri_ops.erasecols = uni_erasecols;
|
|
ri->ri_ops.cursor = uni_cursor;
|
|
ri->ri_ops.putchar = uni_putchar;
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* hardware access
|
|
*/
|
|
static uint8_t
|
|
uni_rd(struct unichromefb_softc *sc, int off, uint8_t idx)
|
|
{
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, idx);
|
|
return bus_space_read_1(sc->sc_iot, sc->sc_ioh, off + 1);
|
|
}
|
|
|
|
static void
|
|
uni_wr(struct unichromefb_softc *sc, int off, uint8_t idx, uint8_t val)
|
|
{
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, idx);
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off + 1, val);
|
|
}
|
|
|
|
static void
|
|
uni_wr_mask(struct unichromefb_softc *sc, int off, uint8_t idx,
|
|
uint8_t val, uint8_t mask)
|
|
{
|
|
uint8_t tmp;
|
|
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, idx);
|
|
tmp = bus_space_read_1(sc->sc_iot, sc->sc_ioh, off + 1);
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, off + 1,
|
|
((val & mask) | (tmp & ~mask)));
|
|
}
|
|
|
|
static void
|
|
uni_wr_dac(struct unichromefb_softc *sc, uint8_t idx,
|
|
uint8_t r, uint8_t g, uint8_t b)
|
|
{
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_INDEX_WRITE, idx);
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_DATA, r);
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_DATA, g);
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, LUT_DATA, b);
|
|
}
|
|
|
|
static void
|
|
uni_wr_x(struct unichromefb_softc *sc, struct io_reg *tbl, int num)
|
|
{
|
|
int i;
|
|
uint8_t tmp;
|
|
|
|
for (i = 0; i < num; i++) {
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, tbl[i].port,
|
|
tbl[i].index);
|
|
tmp = bus_space_read_1(sc->sc_iot, sc->sc_iot,
|
|
tbl[i].port + 1);
|
|
tmp = (tmp & (~tbl[i].mask)) | tbl[i].value;
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, tbl[i].index + 1,
|
|
tmp);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* helpers
|
|
*/
|
|
static struct VideoModeTable *
|
|
uni_getmode(int mode)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < NUM_TOTAL_MODETABLE; i++)
|
|
if (CLE266Modes[i].ModeIndex == mode)
|
|
return &CLE266Modes[i];
|
|
|
|
return NULL;
|
|
}
|
|
|
|
static void
|
|
uni_setmode(struct unichromefb_softc *sc, int idx, int bpp)
|
|
{
|
|
struct VideoModeTable *vtbl;
|
|
struct crt_mode_table *crt;
|
|
int i;
|
|
|
|
/* XXX */
|
|
vtbl = uni_getmode(idx);
|
|
if (vtbl == NULL)
|
|
panic("%s: unsupported mode: %d\n", sc->sc_dev.dv_xname, idx);
|
|
|
|
crt = vtbl->crtc;
|
|
|
|
uni_screen_disable(sc);
|
|
|
|
(void)bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIAStatus);
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, 0);
|
|
|
|
/* XXX assume CN900 for now */
|
|
uni_wr_x(sc, CN900_ModeXregs, NUM_TOTAL_CN900_ModeXregs);
|
|
|
|
uni_crt_disable(sc);
|
|
|
|
/* Fill VPIT params */
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, VPIT.Misc);
|
|
|
|
/* Write sequencer */
|
|
for (i = 1; i <= StdSR; i++) {
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR, i);
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIASR + 1,
|
|
VPIT.SR[i - 1]);
|
|
}
|
|
|
|
uni_set_start(sc);
|
|
|
|
uni_set_crtc(sc, crt, idx, bpp / 8, IGA1);
|
|
|
|
for (i = 0; i < StdGR; i++) {
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAGR, i);
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAGR + 1,
|
|
VPIT.GR[i]);
|
|
}
|
|
|
|
for (i = 0; i < StdAR; i++) {
|
|
(void)bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIAStatus);
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, i);
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR,
|
|
VPIT.AR[i]);
|
|
}
|
|
|
|
(void)bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIAStatus);
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAAR, 0x20);
|
|
|
|
uni_set_crtc(sc, crt, idx, bpp / 8, IGA1);
|
|
/* set crt output path */
|
|
uni_wr_mask(sc, VIASR, SR16, 0x00, BIT6);
|
|
|
|
uni_crt_enable(sc);
|
|
uni_screen_enable(sc);
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_crt_lock(struct unichromefb_softc *sc)
|
|
{
|
|
uni_wr_mask(sc, VIACR, CR11, BIT7, BIT7);
|
|
}
|
|
|
|
static void
|
|
uni_crt_unlock(struct unichromefb_softc *sc)
|
|
{
|
|
uni_wr_mask(sc, VIACR, CR11, 0, BIT7);
|
|
uni_wr_mask(sc, VIACR, CR47, 0, BIT0);
|
|
}
|
|
|
|
static void
|
|
uni_crt_enable(struct unichromefb_softc *sc)
|
|
{
|
|
uni_wr_mask(sc, VIACR, CR36, 0, BIT5+BIT4);
|
|
}
|
|
|
|
static void
|
|
uni_crt_disable(struct unichromefb_softc *sc)
|
|
{
|
|
uni_wr_mask(sc, VIACR, CR36, BIT5+BIT4, BIT5+BIT4);
|
|
}
|
|
|
|
static void
|
|
uni_screen_enable(struct unichromefb_softc *sc)
|
|
{
|
|
uni_wr_mask(sc, VIASR, SR01, 0, BIT5);
|
|
}
|
|
|
|
static void
|
|
uni_screen_disable(struct unichromefb_softc *sc)
|
|
{
|
|
uni_wr_mask(sc, VIASR, SR01, 0x20, BIT5);
|
|
}
|
|
|
|
static void
|
|
uni_set_start(struct unichromefb_softc *sc)
|
|
{
|
|
uni_crt_unlock(sc);
|
|
|
|
uni_wr(sc, VIACR, CR0C, 0x00);
|
|
uni_wr(sc, VIACR, CR0D, 0x00);
|
|
uni_wr(sc, VIACR, CR34, 0x00);
|
|
uni_wr_mask(sc, VIACR, CR48, 0x00, BIT0 + BIT1);
|
|
|
|
uni_wr(sc, VIACR, CR62, 0x00);
|
|
uni_wr(sc, VIACR, CR63, 0x00);
|
|
uni_wr(sc, VIACR, CR64, 0x00);
|
|
uni_wr(sc, VIACR, CRA3, 0x00);
|
|
|
|
uni_crt_lock(sc);
|
|
}
|
|
|
|
static void
|
|
uni_set_crtc(struct unichromefb_softc *sc, struct crt_mode_table *ctbl,
|
|
int mode, int bpp_byte, int iga)
|
|
{
|
|
struct VideoModeTable *vtbl;
|
|
struct display_timing crtreg;
|
|
int i;
|
|
int index;
|
|
int haddr, vaddr;
|
|
uint8_t val;
|
|
uint32_t pll_d_n;
|
|
|
|
index = 0;
|
|
|
|
vtbl = uni_getmode(mode);
|
|
for (i = 0; i < vtbl->mode_array; i++) {
|
|
index = i;
|
|
if (ctbl[i].refresh_rate == 60)
|
|
break;
|
|
}
|
|
|
|
crtreg = ctbl[index].crtc;
|
|
|
|
haddr = crtreg.hor_addr;
|
|
vaddr = crtreg.ver_addr;
|
|
|
|
val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIARMisc);
|
|
if (ctbl[index].h_sync_polarity == NEGATIVE) {
|
|
if (ctbl[index].v_sync_polarity == NEGATIVE)
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc,
|
|
(val & (~(BIT6+BIT7))) | (BIT6+BIT7));
|
|
else
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc,
|
|
(val & (~(BIT6+BIT7))) | (BIT6));
|
|
} else {
|
|
if (ctbl[index].v_sync_polarity == NEGATIVE)
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc,
|
|
(val & (~(BIT6+BIT7))) | (BIT7));
|
|
else
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc,
|
|
(val & (~(BIT6+BIT7))));
|
|
}
|
|
|
|
if (iga == IGA1) {
|
|
uni_crt_unlock(sc);
|
|
uni_wr(sc, VIACR, CR09, 0x00);
|
|
uni_wr_mask(sc, VIACR, CR11, 0x00, BIT4+BIT5+BIT6);
|
|
uni_wr_mask(sc, VIACR, CR17, 0x00, BIT7);
|
|
}
|
|
|
|
uni_load_crtc(sc, crtreg, iga);
|
|
uni_fix_crtc(sc);
|
|
uni_crt_lock(sc);
|
|
uni_wr_mask(sc, VIACR, CR17, 0x80, BIT7);
|
|
|
|
uni_load_offset(sc, haddr, bpp_byte, iga);
|
|
uni_load_fetchcnt(sc, haddr, bpp_byte, iga);
|
|
uni_load_fifo(sc, iga, haddr, vaddr);
|
|
|
|
uni_set_depth(sc, bpp_byte, iga);
|
|
pll_d_n = uni_get_clkval(sc, ctbl[index].clk);
|
|
uni_set_vclk(sc, pll_d_n, iga);
|
|
}
|
|
|
|
static void
|
|
uni_load_crtc(struct unichromefb_softc *sc,
|
|
struct display_timing device_timing, int iga)
|
|
{
|
|
int regnum, val;
|
|
struct io_register *reg;
|
|
int i;
|
|
|
|
regnum = val = 0;
|
|
reg = NULL;
|
|
|
|
uni_crt_unlock(sc);
|
|
|
|
for (i = 0; i < 12; i++) {
|
|
switch (iga) {
|
|
case IGA1:
|
|
switch (i) {
|
|
case H_TOTAL_INDEX:
|
|
val = IGA1_HOR_TOTAL_FORMULA(
|
|
device_timing.hor_total);
|
|
regnum = iga1_crtc_reg.hor_total.reg_num;
|
|
reg = iga1_crtc_reg.hor_total.reg;
|
|
break;
|
|
case H_ADDR_INDEX:
|
|
val = IGA1_HOR_ADDR_FORMULA(
|
|
device_timing.hor_addr);
|
|
regnum = iga1_crtc_reg.hor_addr.reg_num;
|
|
reg = iga1_crtc_reg.hor_addr.reg;
|
|
break;
|
|
case H_BLANK_START_INDEX:
|
|
val = IGA1_HOR_BLANK_START_FORMULA(
|
|
device_timing.hor_blank_start);
|
|
regnum = iga1_crtc_reg.hor_blank_start.reg_num;
|
|
reg = iga1_crtc_reg.hor_blank_start.reg;
|
|
break;
|
|
case H_BLANK_END_INDEX:
|
|
val = IGA1_HOR_BLANK_END_FORMULA(
|
|
device_timing.hor_blank_start,
|
|
device_timing.hor_blank_end);
|
|
regnum = iga1_crtc_reg.hor_blank_end.reg_num;
|
|
reg = iga1_crtc_reg.hor_blank_end.reg;
|
|
break;
|
|
case H_SYNC_START_INDEX:
|
|
val = IGA1_HOR_SYNC_START_FORMULA(
|
|
device_timing.hor_sync_start);
|
|
regnum = iga1_crtc_reg.hor_sync_start.reg_num;
|
|
reg = iga1_crtc_reg.hor_sync_start.reg;
|
|
break;
|
|
case H_SYNC_END_INDEX:
|
|
val = IGA1_HOR_SYNC_END_FORMULA(
|
|
device_timing.hor_sync_start,
|
|
device_timing.hor_sync_end);
|
|
regnum = iga1_crtc_reg.hor_sync_end.reg_num;
|
|
reg = iga1_crtc_reg.hor_sync_end.reg;
|
|
break;
|
|
case V_TOTAL_INDEX:
|
|
val = IGA1_VER_TOTAL_FORMULA(
|
|
device_timing.ver_total);
|
|
regnum = iga1_crtc_reg.ver_total.reg_num;
|
|
reg = iga1_crtc_reg.ver_total.reg;
|
|
break;
|
|
case V_ADDR_INDEX:
|
|
val = IGA1_VER_ADDR_FORMULA(
|
|
device_timing.ver_addr);
|
|
regnum = iga1_crtc_reg.ver_addr.reg_num;
|
|
reg = iga1_crtc_reg.ver_addr.reg;
|
|
break;
|
|
case V_BLANK_START_INDEX:
|
|
val = IGA1_VER_BLANK_START_FORMULA(
|
|
device_timing.ver_blank_start);
|
|
regnum = iga1_crtc_reg.ver_blank_start.reg_num;
|
|
reg = iga1_crtc_reg.ver_blank_start.reg;
|
|
break;
|
|
case V_BLANK_END_INDEX:
|
|
val = IGA1_VER_BLANK_END_FORMULA(
|
|
device_timing.ver_blank_start,
|
|
device_timing.ver_blank_end);
|
|
regnum = iga1_crtc_reg.ver_blank_end.reg_num;
|
|
reg = iga1_crtc_reg.ver_blank_end.reg;
|
|
break;
|
|
case V_SYNC_START_INDEX:
|
|
val = IGA1_VER_SYNC_START_FORMULA(
|
|
device_timing.ver_sync_start);
|
|
regnum = iga1_crtc_reg.ver_sync_start.reg_num;
|
|
reg = iga1_crtc_reg.ver_sync_start.reg;
|
|
break;
|
|
case V_SYNC_END_INDEX:
|
|
val = IGA1_VER_SYNC_END_FORMULA(
|
|
device_timing.ver_sync_start,
|
|
device_timing.ver_sync_end);
|
|
regnum = iga1_crtc_reg.ver_sync_end.reg_num;
|
|
reg = iga1_crtc_reg.ver_sync_end.reg;
|
|
break;
|
|
default:
|
|
printf("%s: unknown index %d while setting up CRTC\n",
|
|
sc->sc_dev.dv_xname, i);
|
|
break;
|
|
}
|
|
break;
|
|
case IGA2:
|
|
printf("%s: %s: IGA2 not supported\n",
|
|
sc->sc_dev.dv_xname, __func__);
|
|
break;
|
|
}
|
|
|
|
uni_load_reg(sc, val, regnum, reg, VIACR);
|
|
}
|
|
|
|
uni_crt_lock(sc);
|
|
}
|
|
|
|
static void
|
|
uni_load_reg(struct unichromefb_softc *sc, int timing, int regnum,
|
|
struct io_register *reg, int type)
|
|
{
|
|
int regmask, bitnum, data;
|
|
int i, j;
|
|
int shift_next_reg;
|
|
int startidx, endidx, cridx;
|
|
uint16_t getbit;
|
|
|
|
bitnum = 0;
|
|
|
|
for (i = 0; i < regnum; i++) {
|
|
regmask = data = 0;
|
|
startidx = reg[i].start_bit;
|
|
endidx = reg[i].end_bit;
|
|
cridx = reg[i].io_addr;
|
|
|
|
shift_next_reg = bitnum;
|
|
|
|
for (j = startidx; j <= endidx; j++) {
|
|
regmask = regmask | (BIT0 << j);
|
|
getbit = (timing & (BIT0 << bitnum));
|
|
data = data | ((getbit >> shift_next_reg) << startidx);
|
|
++bitnum;
|
|
}
|
|
|
|
if (type == VIACR)
|
|
uni_wr_mask(sc, VIACR, cridx, data, regmask);
|
|
else
|
|
uni_wr_mask(sc, VIASR, cridx, data, regmask);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_fix_crtc(struct unichromefb_softc *sc)
|
|
{
|
|
uni_wr_mask(sc, VIACR, CR03, 0x80, BIT7);
|
|
uni_wr(sc, VIACR, CR18, 0xff);
|
|
uni_wr_mask(sc, VIACR, CR07, 0x10, BIT4);
|
|
uni_wr_mask(sc, VIACR, CR09, 0x40, BIT6);
|
|
uni_wr_mask(sc, VIACR, CR35, 0x10, BIT4);
|
|
uni_wr_mask(sc, VIACR, CR33, 0x06, BIT0+BIT1+BIT2);
|
|
uni_wr(sc, VIACR, CR17, 0xe3);
|
|
uni_wr(sc, VIACR, CR08, 0x00);
|
|
uni_wr(sc, VIACR, CR14, 0x00);
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_load_offset(struct unichromefb_softc *sc, int haddr, int bpp, int iga)
|
|
{
|
|
|
|
switch (iga) {
|
|
case IGA1:
|
|
uni_load_reg(sc,
|
|
IGA1_OFFSET_FORMULA(haddr, bpp),
|
|
offset_reg.iga1_offset_reg.reg_num,
|
|
offset_reg.iga1_offset_reg.reg,
|
|
VIACR);
|
|
break;
|
|
default:
|
|
printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname,
|
|
__func__);
|
|
break;
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_load_fetchcnt(struct unichromefb_softc *sc, int haddr, int bpp, int iga)
|
|
{
|
|
|
|
switch (iga) {
|
|
case IGA1:
|
|
uni_load_reg(sc,
|
|
IGA1_FETCH_COUNT_FORMULA(haddr, bpp),
|
|
fetch_count_reg.iga1_fetch_count_reg.reg_num,
|
|
fetch_count_reg.iga1_fetch_count_reg.reg,
|
|
VIASR);
|
|
break;
|
|
default:
|
|
printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname,
|
|
__func__);
|
|
break;
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_load_fifo(struct unichromefb_softc *sc, int iga, int horact, int veract)
|
|
{
|
|
int val, regnum;
|
|
struct io_register *reg;
|
|
int iga1_fifo_max_depth, iga1_fifo_threshold;
|
|
int iga1_fifo_high_threshold, iga1_display_queue_expire_num;
|
|
|
|
reg = NULL;
|
|
iga1_fifo_max_depth = iga1_fifo_threshold = 0;
|
|
iga1_fifo_high_threshold = iga1_display_queue_expire_num = 0;
|
|
|
|
switch (iga) {
|
|
case IGA1:
|
|
/* XXX if (type == CN900) { */
|
|
iga1_fifo_max_depth = CN900_IGA1_FIFO_MAX_DEPTH;
|
|
iga1_fifo_threshold = CN900_IGA1_FIFO_THRESHOLD;
|
|
iga1_fifo_high_threshold = CN900_IGA1_FIFO_HIGH_THRESHOLD;
|
|
if (horact > 1280 && veract > 1024)
|
|
iga1_display_queue_expire_num = 16;
|
|
else
|
|
iga1_display_queue_expire_num =
|
|
CN900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
|
|
/* XXX } */
|
|
|
|
/* set display FIFO depth select */
|
|
val = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
|
|
regnum =
|
|
display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
|
|
reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
|
|
uni_load_reg(sc, val, regnum, reg, VIASR);
|
|
|
|
/* set display FIFO threshold select */
|
|
val = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
|
|
regnum = fifo_threshold_select_reg.iga1_fifo_threshold_select_reg.reg_num;
|
|
reg = fifo_threshold_select_reg.iga1_fifo_threshold_select_reg.reg;
|
|
uni_load_reg(sc, val, regnum, reg, VIASR);
|
|
|
|
/* set display FIFO high threshold select */
|
|
val = IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
|
|
regnum = fifo_high_threshold_select_reg.iga1_fifo_high_threshold_select_reg.reg_num;
|
|
reg = fifo_high_threshold_select_reg.iga1_fifo_high_threshold_select_reg.reg;
|
|
uni_load_reg(sc, val, regnum, reg, VIASR);
|
|
|
|
/* set display queue expire num */
|
|
val = IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA(iga1_display_queue_expire_num);
|
|
regnum = display_queue_expire_num_reg.iga1_display_queue_expire_num_reg.reg_num;
|
|
reg = display_queue_expire_num_reg.iga1_display_queue_expire_num_reg.reg;
|
|
uni_load_reg(sc, val, regnum, reg, VIASR);
|
|
|
|
break;
|
|
default:
|
|
printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname,
|
|
__func__);
|
|
break;
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_set_depth(struct unichromefb_softc *sc, int bpp, int iga)
|
|
{
|
|
switch (iga) {
|
|
case IGA1:
|
|
switch (bpp) {
|
|
case MODE_32BPP:
|
|
uni_wr_mask(sc, VIASR, SR15, 0xae, 0xfe);
|
|
break;
|
|
case MODE_16BPP:
|
|
uni_wr_mask(sc, VIASR, SR15, 0xb6, 0xfe);
|
|
break;
|
|
case MODE_8BPP:
|
|
uni_wr_mask(sc, VIASR, SR15, 0x22, 0xfe);
|
|
break;
|
|
default:
|
|
printf("%s: %s: mode (%d) unsupported\n",
|
|
sc->sc_dev.dv_xname, __func__, bpp);
|
|
}
|
|
break;
|
|
default:
|
|
printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname,
|
|
__func__);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static uint32_t
|
|
uni_get_clkval(struct unichromefb_softc *sc, int clk)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
|
|
if (clk == pll_value[i].clk) {
|
|
/* XXX only CN900 supported for now */
|
|
return pll_value[i].k800_pll;
|
|
}
|
|
}
|
|
|
|
aprint_error("%s: can't find matching PLL value\n",
|
|
sc->sc_dev.dv_xname);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
uni_set_vclk(struct unichromefb_softc *sc, uint32_t clk, int iga)
|
|
{
|
|
uint8_t val;
|
|
|
|
/* hardware reset on */
|
|
uni_wr_mask(sc, VIACR, CR17, 0x00, BIT7);
|
|
|
|
switch (iga) {
|
|
case IGA1:
|
|
/* XXX only CN900 is supported */
|
|
uni_wr(sc, VIASR, SR44, clk / 0x10000);
|
|
uni_wr(sc, VIASR, SR45, (clk & 0xffff) / 0x100);
|
|
uni_wr(sc, VIASR, SR46, clk % 0x100);
|
|
break;
|
|
default:
|
|
printf("%s: %s: only IGA1 is supported\n", sc->sc_dev.dv_xname,
|
|
__func__);
|
|
break;
|
|
}
|
|
|
|
/* hardware reset off */
|
|
uni_wr_mask(sc, VIACR, CR17, 0x80, BIT7);
|
|
|
|
/* reset pll */
|
|
switch (iga) {
|
|
case IGA1:
|
|
uni_wr_mask(sc, VIASR, SR40, 0x02, BIT1);
|
|
uni_wr_mask(sc, VIASR, SR40, 0x00, BIT1);
|
|
break;
|
|
}
|
|
|
|
/* good to go */
|
|
val = bus_space_read_1(sc->sc_iot, sc->sc_ioh, VIARMisc);
|
|
val |= (BIT2+BIT3);
|
|
bus_space_write_1(sc->sc_iot, sc->sc_ioh, VIAWMisc, val);
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_init_dac(struct unichromefb_softc *sc, int iga)
|
|
{
|
|
int i;
|
|
|
|
/* XXX only IGA1 for now */
|
|
uni_wr_mask(sc, VIASR, SR1A, 0x00, BIT0);
|
|
uni_wr_mask(sc, VIASR, SR18, 0x00, BIT7+BIT6);
|
|
for (i = 0; i < 256; i++)
|
|
uni_wr_dac(sc, i,
|
|
palLUT_table[i].red, palLUT_table[i].green, palLUT_table[i].blue);
|
|
|
|
uni_wr_mask(sc, VIASR, SR18, 0xc0, BIT7+BIT6);
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_init_accel(struct unichromefb_softc *sc)
|
|
{
|
|
|
|
/* init 2D engine regs to reset 2D engine */
|
|
MMIO_OUT32(VIA_REG_GEMODE, 0);
|
|
MMIO_OUT32(VIA_REG_SRCPOS, 0);
|
|
MMIO_OUT32(VIA_REG_DSTPOS, 0);
|
|
MMIO_OUT32(VIA_REG_DIMENSION, 0);
|
|
MMIO_OUT32(VIA_REG_PATADDR, 0);
|
|
MMIO_OUT32(VIA_REG_FGCOLOR, 0);
|
|
MMIO_OUT32(VIA_REG_BGCOLOR, 0);
|
|
MMIO_OUT32(VIA_REG_CLIPTL, 0);
|
|
MMIO_OUT32(VIA_REG_CLIPBR, 0);
|
|
MMIO_OUT32(VIA_REG_OFFSET, 0);
|
|
MMIO_OUT32(VIA_REG_KEYCONTROL, 0);
|
|
MMIO_OUT32(VIA_REG_SRCBASE, 0);
|
|
MMIO_OUT32(VIA_REG_DSTBASE, 0);
|
|
MMIO_OUT32(VIA_REG_PITCH, 0);
|
|
MMIO_OUT32(VIA_REG_MONOPAT1, 0);
|
|
|
|
/* init AGP and VQ registers */
|
|
MMIO_OUT32(VIA_REG_TRANSET, 0x00100000);
|
|
MMIO_OUT32(VIA_REG_TRANSPACE, 0x00000000);
|
|
MMIO_OUT32(VIA_REG_TRANSPACE, 0x00333004);
|
|
MMIO_OUT32(VIA_REG_TRANSPACE, 0x60000000);
|
|
MMIO_OUT32(VIA_REG_TRANSPACE, 0x61000000);
|
|
MMIO_OUT32(VIA_REG_TRANSPACE, 0x62000000);
|
|
MMIO_OUT32(VIA_REG_TRANSPACE, 0x63000000);
|
|
MMIO_OUT32(VIA_REG_TRANSPACE, 0x64000000);
|
|
MMIO_OUT32(VIA_REG_TRANSPACE, 0x7d000000);
|
|
|
|
MMIO_OUT32(VIA_REG_TRANSET, 0xfe020000);
|
|
MMIO_OUT32(VIA_REG_TRANSPACE, 0x00000000);
|
|
|
|
/* disable VQ */
|
|
MMIO_OUT32(VIA_REG_TRANSET, 0x00fe0000);
|
|
MMIO_OUT32(VIA_REG_TRANSPACE, 0x00000004);
|
|
MMIO_OUT32(VIA_REG_TRANSPACE, 0x40008c0f);
|
|
MMIO_OUT32(VIA_REG_TRANSPACE, 0x44000000);
|
|
MMIO_OUT32(VIA_REG_TRANSPACE, 0x45080c04);
|
|
MMIO_OUT32(VIA_REG_TRANSPACE, 0x46800408);
|
|
|
|
uni_set_accel_depth(sc);
|
|
|
|
MMIO_OUT32(VIA_REG_SRCBASE, 0);
|
|
MMIO_OUT32(VIA_REG_DSTBASE, 0);
|
|
|
|
MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE |
|
|
(((sc->sc_width * sc->sc_depth >> 3) >> 3) |
|
|
(((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16)));
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_set_accel_depth(struct unichromefb_softc *sc)
|
|
{
|
|
uint32_t gemode;
|
|
|
|
gemode = MMIO_IN32(0x04) & 0xfffffcff;
|
|
|
|
switch (sc->sc_depth) {
|
|
case 32:
|
|
gemode |= VIA_GEM_32bpp;
|
|
break;
|
|
case 16:
|
|
gemode |= VIA_GEM_16bpp;
|
|
break;
|
|
default:
|
|
gemode |= VIA_GEM_8bpp;
|
|
break;
|
|
}
|
|
|
|
/* set colour depth and pitch */
|
|
MMIO_OUT32(VIA_REG_GEMODE, gemode);
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_wait_idle(struct unichromefb_softc *sc)
|
|
{
|
|
int loop = 0;
|
|
|
|
while (!(MMIO_IN32(VIA_REG_STATUS) & VIA_VR_QUEUE_BUSY) &&
|
|
(loop++ < MAXLOOP))
|
|
;
|
|
|
|
while ((MMIO_IN32(VIA_REG_STATUS) &
|
|
(VIA_CMD_RGTR_BUSY | VIA_2D_ENG_BUSY | VIA_3D_ENG_BUSY)) &&
|
|
(loop++ < MAXLOOP))
|
|
;
|
|
|
|
if (loop >= MAXLOOP)
|
|
aprint_error("%s: engine stall\n", sc->sc_dev.dv_xname);
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_fillrect(struct unichromefb_softc *sc, int x, int y, int width,
|
|
int height, int colour)
|
|
{
|
|
|
|
uni_wait_idle(sc);
|
|
|
|
MMIO_OUT32(VIA_REG_SRCPOS, 0);
|
|
MMIO_OUT32(VIA_REG_SRCBASE, 0);
|
|
MMIO_OUT32(VIA_REG_DSTBASE, 0);
|
|
MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE |
|
|
(((sc->sc_width * sc->sc_depth >> 3) >> 3) |
|
|
(((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16)));
|
|
MMIO_OUT32(VIA_REG_DSTPOS, ((y << 16) | x));
|
|
MMIO_OUT32(VIA_REG_DIMENSION,
|
|
(((height - 1) << 16) | (width - 1)));
|
|
MMIO_OUT32(VIA_REG_FGCOLOR, colour);
|
|
MMIO_OUT32(VIA_REG_GECMD, (0x01 | 0x2000 | 0xf0 << 24));
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_rectinvert(struct unichromefb_softc *sc, int x, int y, int width,
|
|
int height)
|
|
{
|
|
|
|
uni_wait_idle(sc);
|
|
|
|
MMIO_OUT32(VIA_REG_SRCPOS, 0);
|
|
MMIO_OUT32(VIA_REG_SRCBASE, 0);
|
|
MMIO_OUT32(VIA_REG_DSTBASE, 0);
|
|
MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE |
|
|
(((sc->sc_width * sc->sc_depth >> 3) >> 3) |
|
|
(((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16)));
|
|
MMIO_OUT32(VIA_REG_DSTPOS, ((y << 16) | x));
|
|
MMIO_OUT32(VIA_REG_DIMENSION,
|
|
(((height - 1) << 16) | (width - 1)));
|
|
MMIO_OUT32(VIA_REG_GECMD, (0x01 | 0x2000 | 0x55 << 24));
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_bitblit(struct unichromefb_softc *sc, int xs, int ys, int xd, int yd, int width, int height)
|
|
{
|
|
uint32_t dir;
|
|
|
|
dir = 0;
|
|
|
|
if (ys < yd) {
|
|
yd += height - 1;
|
|
ys += height - 1;
|
|
dir |= 0x4000;
|
|
}
|
|
|
|
if (xs < xd) {
|
|
xd += width - 1;
|
|
xs += width - 1;
|
|
dir |= 0x8000;
|
|
}
|
|
|
|
uni_wait_idle(sc);
|
|
|
|
MMIO_OUT32(VIA_REG_SRCBASE, 0);
|
|
MMIO_OUT32(VIA_REG_DSTBASE, 0);
|
|
MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE |
|
|
(((sc->sc_width * sc->sc_depth >> 3) >> 3) |
|
|
(((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16)));
|
|
MMIO_OUT32(VIA_REG_SRCPOS, ys << 16 | xs);
|
|
MMIO_OUT32(VIA_REG_DSTPOS, yd << 16 | xd);
|
|
MMIO_OUT32(VIA_REG_DIMENSION, ((height - 1) << 16) | (width - 1));
|
|
MMIO_OUT32(VIA_REG_GECMD, (0x01 | dir | (0xcc << 24)));
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_setup_mono(struct unichromefb_softc *sc, int xd, int yd, int width, int height,
|
|
uint32_t fg, uint32_t bg)
|
|
{
|
|
|
|
uni_wait_idle(sc);
|
|
|
|
MMIO_OUT32(VIA_REG_SRCBASE, 0);
|
|
MMIO_OUT32(VIA_REG_DSTBASE, 0);
|
|
MMIO_OUT32(VIA_REG_PITCH, VIA_PITCH_ENABLE |
|
|
(((sc->sc_width * sc->sc_depth >> 3) >> 3) |
|
|
(((sc->sc_width * sc->sc_depth >> 3) >> 3) << 16)));
|
|
MMIO_OUT32(VIA_REG_SRCPOS, 0);
|
|
MMIO_OUT32(VIA_REG_DSTPOS, (yd << 16) | xd);
|
|
MMIO_OUT32(VIA_REG_DIMENSION, ((height - 1) << 16) | (width - 1));
|
|
MMIO_OUT32(VIA_REG_FGCOLOR, fg);
|
|
MMIO_OUT32(VIA_REG_BGCOLOR, bg);
|
|
MMIO_OUT32(VIA_REG_GECMD, 0xcc020142);
|
|
|
|
return;
|
|
}
|
|
|
|
#if notyet
|
|
static void
|
|
uni_cursor_show(struct unichromefb_softc *sc)
|
|
{
|
|
uint32_t val;
|
|
|
|
val = MMIO_IN32(VIA_REG_CURSOR_MODE);
|
|
val |= 1;
|
|
MMIO_OUT32(VIA_REG_CURSOR_MODE, val);
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_cursor_hide(struct unichromefb_softc *sc)
|
|
{
|
|
uint32_t val;
|
|
|
|
val = MMIO_IN32(VIA_REG_CURSOR_MODE);
|
|
val &= 0xfffffffe;
|
|
MMIO_OUT32(VIA_REG_CURSOR_MODE, val);
|
|
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* rasops glue
|
|
*/
|
|
static void
|
|
uni_copycols(void *opaque, int row, int srccol, int dstcol, int ncols)
|
|
{
|
|
struct rasops_info *ri;
|
|
struct vcons_screen *scr;
|
|
struct unichromefb_softc *sc;
|
|
int xs, xd, y, width, height;
|
|
|
|
ri = (struct rasops_info *)opaque;
|
|
scr = (struct vcons_screen *)ri->ri_hw;
|
|
sc = (struct unichromefb_softc *)scr->scr_cookie;
|
|
|
|
if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) {
|
|
xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol;
|
|
xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol;
|
|
y = ri->ri_yorigin + ri->ri_font->fontheight * row;
|
|
width = ri->ri_font->fontwidth * ncols;
|
|
height = ri->ri_font->fontheight;
|
|
uni_bitblit(sc, xs, y, xd, y, width, height);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_copyrows(void *opaque, int srcrow, int dstrow, int nrows)
|
|
{
|
|
struct rasops_info *ri;
|
|
struct vcons_screen *scr;
|
|
struct unichromefb_softc *sc;
|
|
int x, ys, yd, width, height;
|
|
|
|
ri = (struct rasops_info *)opaque;
|
|
scr = (struct vcons_screen *)ri->ri_hw;
|
|
sc = (struct unichromefb_softc *)scr->scr_cookie;
|
|
|
|
if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) {
|
|
x = ri->ri_xorigin;
|
|
ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow;
|
|
yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow;
|
|
width = ri->ri_emuwidth;
|
|
height = ri->ri_font->fontheight * nrows;
|
|
uni_bitblit(sc, x, ys, x, yd, width, height);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_erasecols(void *opaque, int row, int startcol, int ncols, long fillattr)
|
|
{
|
|
struct rasops_info *ri;
|
|
struct vcons_screen *scr;
|
|
struct unichromefb_softc *sc;
|
|
int x, y, width, height, fg, bg, ul;
|
|
|
|
ri = (struct rasops_info *)opaque;
|
|
scr = (struct vcons_screen *)ri->ri_hw;
|
|
sc = (struct unichromefb_softc *)scr->scr_cookie;
|
|
|
|
if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) {
|
|
x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol;
|
|
y = ri->ri_yorigin + ri->ri_font->fontheight * row;
|
|
width = ri->ri_font->fontwidth * ncols;
|
|
height = ri->ri_font->fontheight;
|
|
rasops_unpack_attr(fillattr, &fg, &bg, &ul);
|
|
uni_fillrect(sc, x, y, width, height, ri->ri_devcmap[bg]);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_eraserows(void *opaque, int row, int nrows, long fillattr)
|
|
{
|
|
struct rasops_info *ri;
|
|
struct vcons_screen *scr;
|
|
struct unichromefb_softc *sc;
|
|
int x, y, width, height, fg, bg, ul;
|
|
|
|
ri = (struct rasops_info *)opaque;
|
|
scr = (struct vcons_screen *)ri->ri_hw;
|
|
sc = (struct unichromefb_softc *)scr->scr_cookie;
|
|
|
|
if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) {
|
|
rasops_unpack_attr(fillattr, &fg, &bg, &ul);
|
|
if ((row == 0) && (nrows == ri->ri_rows)) {
|
|
/* clear the whole screen */
|
|
uni_fillrect(sc, 0, 0, ri->ri_width,
|
|
ri->ri_height, ri->ri_devcmap[bg]);
|
|
} else {
|
|
x = ri->ri_xorigin;
|
|
y = ri->ri_yorigin + ri->ri_font->fontheight * row;
|
|
width = ri->ri_emuwidth;
|
|
height = ri->ri_font->fontheight * nrows;
|
|
uni_fillrect(sc, x, y, width, height,
|
|
ri->ri_devcmap[bg]);
|
|
}
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_cursor(void *opaque, int on, int row, int col)
|
|
{
|
|
struct rasops_info *ri;
|
|
struct vcons_screen *scr;
|
|
struct unichromefb_softc *sc;
|
|
int x, y, wi, he;
|
|
|
|
ri = (struct rasops_info *)opaque;
|
|
scr = (struct vcons_screen *)ri->ri_hw;
|
|
sc = (struct unichromefb_softc *)scr->scr_cookie;
|
|
|
|
uni_wait_idle(sc);
|
|
|
|
wi = ri->ri_font->fontwidth;
|
|
he = ri->ri_font->fontheight;
|
|
|
|
if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) {
|
|
x = ri->ri_ccol * wi + ri->ri_xorigin;
|
|
y = ri->ri_crow * he + ri->ri_yorigin;
|
|
if (ri->ri_flg & RI_CURSOR) {
|
|
uni_rectinvert(sc, x, y, wi, he);
|
|
ri->ri_flg &= ~RI_CURSOR;
|
|
}
|
|
ri->ri_crow = row;
|
|
ri->ri_ccol = col;
|
|
if (on) {
|
|
x = ri->ri_ccol * wi + ri->ri_xorigin;
|
|
y = ri->ri_crow * he + ri->ri_yorigin;
|
|
uni_rectinvert(sc, x, y, wi, he);
|
|
ri->ri_flg |= RI_CURSOR;
|
|
}
|
|
} else {
|
|
ri->ri_flg &= ~RI_CURSOR;
|
|
ri->ri_crow = row;
|
|
ri->ri_ccol = col;
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
uni_putchar(void *opaque, int row, int col, u_int c, long attr)
|
|
{
|
|
struct rasops_info *ri;
|
|
struct vcons_screen *scr;
|
|
struct unichromefb_softc *sc;
|
|
|
|
ri = (struct rasops_info *)opaque;
|
|
scr = (struct vcons_screen *)ri->ri_hw;
|
|
sc = (struct unichromefb_softc *)scr->scr_cookie;
|
|
|
|
if (sc->sc_wsmode == WSDISPLAYIO_MODE_EMUL) {
|
|
uint32_t *data;
|
|
int fg, bg, ul, uc, i;
|
|
int x, y, wi, he;
|
|
|
|
wi = ri->ri_font->fontwidth;
|
|
he = ri->ri_font->fontheight;
|
|
|
|
if (!CHAR_IN_FONT(c, ri->ri_font))
|
|
return;
|
|
|
|
rasops_unpack_attr(attr, &fg, &bg, &ul);
|
|
x = ri->ri_xorigin + col * wi;
|
|
y = ri->ri_yorigin + row * he;
|
|
if (c == 0x20)
|
|
uni_fillrect(sc, x, y, wi, he, ri->ri_devcmap[bg]);
|
|
else {
|
|
uc = c - ri->ri_font->firstchar;
|
|
data = (uint32_t *)((uint8_t *)ri->ri_font->data +
|
|
uc * ri->ri_fontscale);
|
|
uni_setup_mono(sc, x, y, wi, he,
|
|
ri->ri_devcmap[fg], ri->ri_devcmap[bg]);
|
|
for (i = 0; i < (wi * he) / 4; i++) {
|
|
MMIO_OUT32(VIA_MMIO_BLTBASE, *data);
|
|
data++;
|
|
}
|
|
}
|
|
}
|
|
|
|
return;
|
|
}
|