283 lines
7.5 KiB
C
283 lines
7.5 KiB
C
/* $NetBSD: tcds_dma.c,v 1.21 1997/09/02 13:20:41 thorpej Exp $ */
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/*
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* Copyright (c) 1994 Peter Galbavy. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: tcds_dma.c,v 1.21 1997/09/02 13:20:41 thorpej Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <dev/tc/tcvar.h>
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#include <alpha/tc/tcdsreg.h>
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#include <alpha/tc/tcdsvar.h>
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#include <alpha/tc/ascvar.h>
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void
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tcds_dma_reset(sc)
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struct tcds_slotconfig *sc;
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{
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/* TCDS SCSI disable/reset/enable. */
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tcds_scsi_reset(sc); /* XXX */
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sc->sc_active = 0; /* and of course we aren't */
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}
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int
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tcds_dma_isintr(sc)
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struct tcds_slotconfig *sc;
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{
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int x;
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x = tcds_scsi_isintr(sc, 1);
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/* XXX */
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return x;
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}
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/*
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* Pseudo (chained) interrupt from the asc driver to kick the
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* current running DMA transfer. I am replying on ascintr() to
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* pickup and clean errors for now
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*
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* return 1 if it was a DMA continue.
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*/
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int
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tcds_dma_intr(sc)
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struct tcds_slotconfig *sc;
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{
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struct ncr53c9x_softc *nsc = &sc->sc_asc->sc_ncr53c9x;
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u_int32_t dud;
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int trans = 0, resid = 0;
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u_int32_t *addr, dudmask;
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u_char tcl, tcm, tch;
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NCR_DMA(("tcds_dma %d: intr", sc->sc_slot));
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if (tcds_scsi_iserr(sc))
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return (0);
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/* This is an "assertion" :) */
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if (sc->sc_active == 0)
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panic("dmaintr: DMA wasn't active");
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/* DMA has stopped */
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tcds_dma_enable(sc, 0);
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sc->sc_active = 0;
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if (sc->sc_dmasize == 0) {
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/* A "Transfer Pad" operation completed */
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tcl = NCR_READ_REG(nsc, NCR_TCL);
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tcm = NCR_READ_REG(nsc, NCR_TCM);
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NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
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tcl | (tcm << 8), tcl, tcm));
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return 0;
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}
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if (!sc->sc_iswrite &&
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(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
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NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid));
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DELAY(1);
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}
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resid += (tcl = NCR_READ_REG(nsc, NCR_TCL));
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resid += (tcm = NCR_READ_REG(nsc, NCR_TCM)) << 8;
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if (nsc->sc_rev == NCR_VARIANT_ESP200)
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resid += (tch = NCR_READ_REG(nsc, NCR_TCH)) << 16;
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else
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tch = 0;
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if (resid == 0 && (nsc->sc_rev <= NCR_VARIANT_ESP100A) &&
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(nsc->sc_espstat & NCRSTAT_TC) == 0)
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resid = 65536;
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trans = sc->sc_dmasize - resid;
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if (trans < 0) { /* transferred < 0 ? */
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printf("tcds_dma %d: xfer (%d) > req (%ld)\n",
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sc->sc_slot, trans, sc->sc_dmasize);
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trans = sc->sc_dmasize;
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}
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NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
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tcl, tcm, tch, trans, resid));
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/*
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* Clean up unaligned DMAs into main memory.
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*/
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if (sc->sc_iswrite) {
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/* Handle unaligned starting address, length. */
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dud = *sc->sc_dud0;
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if ((dud & TCDS_DUD0_VALIDBITS) != 0) {
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addr = (u_int32_t *)
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((vm_offset_t)sc->sc_dmaaddr & ~0x3);
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dudmask = 0;
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if (dud & TCDS_DUD0_VALID00)
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panic("tcds_dma: dud0 byte 0 valid");
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if (dud & TCDS_DUD0_VALID01)
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dudmask |= TCDS_DUD_BYTE01;
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if (dud & TCDS_DUD0_VALID10)
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dudmask |= TCDS_DUD_BYTE10;
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#ifdef DIAGNOSTIC
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if (dud & TCDS_DUD0_VALID11)
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dudmask |= TCDS_DUD_BYTE11;
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#endif
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NCR_DMA(("dud0 at 0x%p dudmask 0x%x\n",
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addr, dudmask));
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addr = (u_int32_t *)ALPHA_PHYS_TO_K0SEG((vm_offset_t)addr);
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*addr = (*addr & ~dudmask) | (dud & dudmask);
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}
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dud = *sc->sc_dud1;
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if ((dud & TCDS_DUD1_VALIDBITS) != 0) {
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addr = (u_int32_t *)
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((vm_offset_t)*sc->sc_sda << 2);
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dudmask = 0;
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if (dud & TCDS_DUD1_VALID00)
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dudmask |= TCDS_DUD_BYTE00;
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if (dud & TCDS_DUD1_VALID01)
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dudmask |= TCDS_DUD_BYTE01;
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if (dud & TCDS_DUD1_VALID10)
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dudmask |= TCDS_DUD_BYTE10;
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#ifdef DIAGNOSTIC
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if (dud & TCDS_DUD1_VALID11)
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panic("tcds_dma: dud1 byte 3 valid");
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#endif
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NCR_DMA(("dud1 at 0x%p dudmask 0x%x\n",
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addr, dudmask));
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addr = (u_int32_t *)ALPHA_PHYS_TO_K0SEG((vm_offset_t)addr);
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*addr = (*addr & ~dudmask) | (dud & dudmask);
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}
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/* XXX deal with saved residual byte? */
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}
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*sc->sc_dmalen -= trans;
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*sc->sc_dmaaddr += trans;
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#if 0 /* this is not normal operation just yet */
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if (*sc->sc_dmalen == 0 ||
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nsc->sc_phase != nsc->sc_prevphase)
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return 0;
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/* and again */
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dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, sc->sc_iswrite);
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return 1;
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#endif
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return 0;
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}
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#define DMAMAX(a) (0x02000 - ((a) & 0x1fff))
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/*
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* start a dma transfer or keep it going
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*/
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int
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tcds_dma_setup(sc, addr, len, datain, dmasize)
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struct tcds_slotconfig *sc;
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caddr_t *addr;
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size_t *len, *dmasize;
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int datain; /* DMA into main memory */
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{
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u_int32_t dic;
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size_t size;
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sc->sc_dmaaddr = addr;
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sc->sc_dmalen = len;
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sc->sc_iswrite = datain;
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NCR_DMA(("tcds_dma %d: start %ld@%p,%d\n", sc->sc_slot, *sc->sc_dmalen, *sc->sc_dmaaddr, sc->sc_iswrite));
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/*
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* the rules say we cannot transfer more than the limit
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* of this DMA chip (64k) and we cannot cross a 8k boundary.
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*/
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size = min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
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*dmasize = sc->sc_dmasize = size;
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NCR_DMA(("dma_start: dmasize = %ld\n", sc->sc_dmasize));
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/* Load address, set/clear unaligned transfer and read/write bits. */
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/* XXX PICK AN ADDRESS TYPE, AND STICK TO IT! */
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if ((u_long)*addr > VM_MIN_KERNEL_ADDRESS) {
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*sc->sc_sda = vatopa((u_long)*addr) >> 2;
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} else {
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*sc->sc_sda = ALPHA_K0SEG_TO_PHYS((u_long)*addr) >> 2;
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}
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alpha_mb();
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dic = *sc->sc_dic;
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dic &= ~TCDS_DIC_ADDRMASK;
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dic |= (vm_offset_t)*addr & TCDS_DIC_ADDRMASK;
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if (datain)
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dic |= TCDS_DIC_WRITE;
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else
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dic &= ~TCDS_DIC_WRITE;
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*sc->sc_dic = dic;
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alpha_mb();
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return (0);
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}
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void
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tcds_dma_go(sc)
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struct tcds_slotconfig *sc;
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{
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/* mark unit as DMA-active */
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sc->sc_active = 1;
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/* Start DMA */
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tcds_dma_enable(sc, 1);
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}
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int
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tcds_dma_isactive(sc)
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struct tcds_slotconfig *sc;
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{
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return (sc->sc_active);
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}
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