258 lines
6.5 KiB
C
258 lines
6.5 KiB
C
/* $NetBSD: if_ath_cardbus.c,v 1.45 2011/10/07 20:47:42 dyoung Exp $ */
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/*
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* Copyright (c) 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* CardBus bus front-end for the AR5001 Wireless LAN 802.11a/b/g CardBus.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_ath_cardbus.c,v 1.45 2011/10/07 20:47:42 dyoung Exp $");
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#include "opt_inet.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/ioctl.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <machine/endian.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_ether.h>
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#include <net80211/ieee80211_netbsd.h>
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#include <net80211/ieee80211_var.h>
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/if_inarp.h>
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#endif
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#include <sys/bus.h>
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#include <sys/intr.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/mii_bitbang.h>
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#include <dev/ic/ath_netbsd.h>
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#include <dev/ic/athvar.h>
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#include <external/isc/atheros_hal/dist/ah.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/cardbus/cardbusvar.h>
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#include <dev/pci/pcidevs.h>
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/*
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* PCI configuration space registers
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*/
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#define ATH_PCI_MMBA PCI_BAR(0) /* memory mapped base */
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struct ath_cardbus_softc {
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struct ath_softc sc_ath;
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/* CardBus-specific goo. */
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void *sc_ih; /* interrupt handle */
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cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */
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pcitag_t sc_tag; /* our CardBus tag */
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bus_size_t sc_mapsize; /* the size of mapped bus space region */
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pcireg_t sc_bar_val; /* value of the BAR */
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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};
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int ath_cardbus_match(device_t, cfdata_t, void *);
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void ath_cardbus_attach(device_t, device_t, void *);
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int ath_cardbus_detach(device_t, int);
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CFATTACH_DECL_NEW(ath_cardbus, sizeof(struct ath_cardbus_softc),
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ath_cardbus_match, ath_cardbus_attach, ath_cardbus_detach, NULL);
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void ath_cardbus_setup(struct ath_cardbus_softc *);
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static bool
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ath_cardbus_suspend(device_t self, const pmf_qual_t *qual)
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{
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struct ath_cardbus_softc *csc = device_private(self);
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ath_suspend(&csc->sc_ath);
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if (csc->sc_ih != NULL) {
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Cardbus_intr_disestablish(csc->sc_ct, csc->sc_ih);
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csc->sc_ih = NULL;
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}
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return true;
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}
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static bool
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ath_cardbus_resume(device_t self, const pmf_qual_t *qual)
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{
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struct ath_cardbus_softc *csc = device_private(self);
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csc->sc_ih = Cardbus_intr_establish(csc->sc_ct,
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IPL_NET, ath_intr, &csc->sc_ath);
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if (csc->sc_ih == NULL) {
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aprint_error_dev(self,
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"unable to establish interrupt\n");
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return false;
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}
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return ath_resume(&csc->sc_ath);
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}
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int
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ath_cardbus_match(device_t parent, cfdata_t match, void *aux)
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{
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struct cardbus_attach_args *ca = aux;
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const char *devname;
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devname = ath_hal_probe(PCI_VENDOR(ca->ca_id), PCI_PRODUCT(ca->ca_id));
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if (devname)
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return 1;
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return 0;
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}
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void
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ath_cardbus_attach(device_t parent, device_t self, void *aux)
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{
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struct ath_cardbus_softc *csc = device_private(self);
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struct ath_softc *sc = &csc->sc_ath;
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struct cardbus_attach_args *ca = aux;
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cardbus_devfunc_t ct = ca->ca_ct;
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bus_addr_t adr;
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sc->sc_dev = self;
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sc->sc_dmat = ca->ca_dmat;
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csc->sc_ct = ct;
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csc->sc_tag = ca->ca_tag;
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aprint_normal("\n");
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/*
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* Map the device.
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*/
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if (Cardbus_mapreg_map(ct, ATH_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0,
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&csc->sc_iot, &csc->sc_ioh, &adr, &csc->sc_mapsize) == 0) {
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csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
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} else {
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aprint_error_dev(self, "unable to map device registers\n");
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return;
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}
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sc->sc_st = HALTAG(csc->sc_iot);
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sc->sc_sh = HALHANDLE(csc->sc_ioh);
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/*
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* Set up the PCI configuration registers.
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*/
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ath_cardbus_setup(csc);
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/*
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* Finish off the attach.
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*/
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if (ath_attach(PCI_PRODUCT(ca->ca_id), sc) != 0)
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return;
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if (pmf_device_register(self,
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ath_cardbus_suspend, ath_cardbus_resume)) {
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pmf_class_network_register(self, &sc->sc_if);
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pmf_device_suspend(self, &sc->sc_qual);
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} else
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aprint_error_dev(self, "couldn't establish power handler\n");
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}
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int
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ath_cardbus_detach(device_t self, int flags)
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{
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struct ath_cardbus_softc *csc = device_private(self);
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struct ath_softc *sc = &csc->sc_ath;
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struct cardbus_devfunc *ct = csc->sc_ct;
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int rv;
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#if defined(DIAGNOSTIC)
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if (ct == NULL)
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panic("%s: data structure lacks", device_xname(sc->sc_dev));
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#endif
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rv = ath_detach(sc);
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if (rv)
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return (rv);
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pmf_device_deregister(self);
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/*
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* Unhook the interrupt handler.
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*/
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if (csc->sc_ih != NULL) {
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Cardbus_intr_disestablish(ct, csc->sc_ih);
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csc->sc_ih = NULL;
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}
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/*
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* Release bus space and close window.
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*/
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Cardbus_mapreg_unmap(ct, ATH_PCI_MMBA, csc->sc_iot, csc->sc_ioh,
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csc->sc_mapsize);
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return (0);
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}
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void
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ath_cardbus_setup(struct ath_cardbus_softc *csc)
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{
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cardbus_devfunc_t ct = csc->sc_ct;
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int rc;
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pcireg_t reg;
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if ((rc = cardbus_set_powerstate(ct, csc->sc_tag, PCI_PWR_D0)) != 0)
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aprint_debug("%s: cardbus_set_powerstate %d\n", __func__, rc);
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/* Program the BAR. */
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Cardbus_conf_write(ct, csc->sc_tag, ATH_PCI_MMBA, csc->sc_bar_val);
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/* Enable the appropriate bits in the PCI CSR. */
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reg = Cardbus_conf_read(ct, csc->sc_tag,
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PCI_COMMAND_STATUS_REG);
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reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
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Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
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}
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