152 lines
7.6 KiB
C
152 lines
7.6 KiB
C
/* $NetBSD: sysioreg.h,v 1.1.1.1 1998/06/20 04:58:52 eeh Exp $ */
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/*
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* Copyright (c) 1996
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* The President and Fellows of Harvard College. All rights reserved.
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* Copyright (c) 1995 Paul Kranenburg
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Aaron Brown and
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* Harvard University.
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* This product includes software developed by Paul Kranenburg.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* sysio is the sun5/sun4u SBUS controller/DMA/IOMMU/etc. ASIC.
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*/
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struct sysioreg {
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struct upareg {
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u_int64_t upa_portid; /* UPA port ID register */ /* 1fe.0000.0000 */
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u_int64_t upa_config; /* UPA config register */ /* 1fe.0000.0008 */
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} upa;
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u_int64_t sys_csr; /* SYSIO control/status register */ /* 1fe.0000.0010 */
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u_int64_t pad0;
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u_int64_t sys_ecccr; /* ECC control register */ /* 1fe.0000.0020 */
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u_int64_t reserved; /* 1fe.0000.0028 */
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u_int64_t sys_ue_afsr; /* Uncorrectable Error AFSR */ /* 1fe.0000.0030 */
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u_int64_t sys_ue_afar; /* Uncorrectable Error AFAR */ /* 1fe.0000.0038 */
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u_int64_t sys_ce_afsr; /* Correctable Error AFSR */ /* 1fe.0000.0040 */
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u_int64_t sys_ce_afar; /* Correctable Error AFAR */ /* 1fe.0000.0048 */
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char pad1[0x2000 - 0x50];
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struct sbusreg {
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u_int64_t sys_sbus_cr; /* SBUS Control Register */ /* 1fe.0000.2000 */
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u_int64_t reserved; /* 1fe.0000.2008 */
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u_int64_t sys_sbus_afsr; /* SBUS AFSR */ /* 1fe.0000.2010 */
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u_int64_t sys_sbus_afar; /* SBUS AFAR */ /* 1fe.0000.2018 */
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u_int64_t sys_sbus_config0; /* SBUS Slot 0 config register */ /* 1fe.0000.2020 */
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u_int64_t sys_sbus_config1; /* SBUS Slot 1 config register */ /* 1fe.0000.2028 */
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u_int64_t sys_sbus_config2; /* SBUS Slot 2 config register */ /* 1fe.0000.2030 */
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u_int64_t sys_sbus_config3; /* SBUS Slot 3 config register */ /* 1fe.0000.2038 */
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u_int64_t sys_sbus_config13; /* Slot 13 config register <audio> */ /* 1fe.0000.2040 */
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u_int64_t sys_sbus_config14; /* Slot 14 config register <Macio> */ /* 1fe.0000.2048 */
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u_int64_t sys_sbus_config15; /* Slot 15 config register <slavio> */ /* 1fe.0000.2050 */
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} sbus;
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char pad2[0x400 - 0x50];
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struct iommureg {
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u_int64_t iommu_cr; /* IOMMU control register */ /* 1fe.0000.2400 */
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u_int64_t iommu_tsb; /* IOMMU TSB base register */ /* 1fe.0000.2408 */
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u_int64_t iommu_flush; /* IOMMU flush register */ /* 1fe.0000.2410 */
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} iommu;
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u_int64_t strbuf_ctl; /* streaming buffer control reg */ /* 1fe.0000.2800 */
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u_int64_t strbuf_pgflush; /* streaming buffer page flush */ /* 1fe.0000.2808 */
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u_int64_t strbuf_flushsync; /* streaming buffer flush sync */ /* 1fe.0000.2810 */
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u_int64_t sbus_slot0_int; /* SBUS slot 0 interrupt map reg */ /* 1fe.0000.2c00 */
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u_int64_t sbus_slot1_int; /* SBUS slot 1 interrupt map reg */ /* 1fe.0000.2c08 */
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u_int64_t sbus_slot2_int; /* SBUS slot 2 interrupt map reg */ /* 1fe.0000.2c10 */
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u_int64_t sbus_slot3_int; /* SBUS slot 3 interrupt map reg */ /* 1fe.0000.2c18 */
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u_int64_t scsi_int_map; /* SCSI interrupt map reg */ /* 1fe.0000.3000 */
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u_int64_t ether_int_map; /* ethernet interrupt map reg */ /* 1fe.0000.3008 */
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u_int64_t bpp_int_map; /* parallel interrupt map reg */ /* 1fe.0000.3010 */
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u_int64_t audio_int_map; /* audio interrupt map reg */ /* 1fe.0000.3018 */
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u_int64_t power_int_map; /* power fail interrupt map reg */ /* 1fe.0000.3020 */
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u_int64_t ser_kbd_ms_int_map; /* serial/kbd/mouse interrupt map reg *//* 1fe.0000.3028 */
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u_int64_t fd_int_map; /* floppy interrupt map reg */ /* 1fe.0000.3030 */
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u_int64_t therm_int_map; /* thermal warn interrupt map reg */ /* 1fe.0000.3038 */
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u_int64_t kbd_int_map; /* kbd [unused] interrupt map reg */ /* 1fe.0000.3040 */
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u_int64_t mouse_int_map; /* mouse [unused] interrupt map reg */ /* 1fe.0000.3048 */
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u_int64_t serial_int_map; /* second serial interrupt map reg */ /* 1fe.0000.3050 */
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u_int64_t timer0_int_map; /* timer 0 interrupt map reg */ /* 1fe.0000.3060 */
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u_int64_t timer1_int_map; /* timer 1 interrupt map reg */ /* 1fe.0000.3068 */
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u_int64_t ue_int_map; /* UE interrupt map reg */ /* 1fe.0000.3070 */
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u_int64_t ce_int_map; /* CE interrupt map reg */ /* 1fe.0000.3078 */
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u_int64_t sbus_int_map; /* SBUS error interrupt map reg */ /* 1fe.0000.3080 */
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u_int64_t pwrmgt_int_map; /* power mgmt wake interrupt map reg */ /* 1fe.0000.3088 */
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u_int64_t upagr_int_map; /* UPA graphics interrupt map reg */ /* 1fe.0000.3090 */
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u_int64_t reserved_int_map; /* SCSI interrupt map reg */ /* 1fe.0000.3098 */
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u_int64_t sys_svadiag; /* SBUS virtual addr diag reg */ /* 1fe.0000.4400 */
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u_int64_t iommu_queue_diag[16]; /* IOMMU LRU queue diag */ /* 1fe.0000.4500-457f */
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u_int64_t tlb_tag_diag[16]; /* TLB tag diag */ /* 1fe.0000.4580-45ff */
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u_int64_t tlb_data_diag[32]; /* TLB data RAM diag */ /* 1fe.0000.4600-46ff */
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u_int64_t strbuf_data_diag[128]; /* streaming buffer data RAM diag */ /* 1fe.0000.5000-53f8 */
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u_int64_t strbuf_error_diag[128]; /* streaming buffer error status diag *//* 1fe.0000.5400-57f8 */
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u_int64_t strbuf_pg_tag_diag[16]; /* streaming buffer page tag diag */ /* 1fe.0000.5800-5878 */
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u_int64_t strbuf_ln_tag_diag[16]; /* streaming buffer line tag diag */ /* 1fe.0000.5900-5978 */
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};
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#define IOMMU_CTL_IMPL 0xf0000000
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#define IOMMU_CTL_VER 0x0f000000
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#define IOMMU_CTL_RSVD1 0x00ffffe0
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#define IOMMU_CTL_RANGE 0x0000001c
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#define IOMMU_CTL_RANGESHFT 2
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#define IOMMU_CTL_RSVD2 0x00000002
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#define IOMMU_CTL_ME 0x00000001
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#define IOMMU_BAR_IBA 0xfffffc00
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#define IOMMU_BAR_IBASHFT 10
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/* Flushpage fields */
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#define IOMMU_FLPG_VADDR 0xfffff000
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#define IOMMU_FLUSH_MASK 0xfffff000
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#define IOMMU_FLUSHPAGE(sc, va) do { \
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(sc)->sc_reg->io_flushpage = (va) & IOMMU_FLUSH_MASK; \
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} while (0);
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#define IOMMU_FLUSHALL(sc) do { \
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(sc)->sc_reg->io_flashclear = 0; \
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} while (0)
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/* to pte.h ? */
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typedef u_int32_t iopte_t;
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#define IOPTE_PPN 0xffffff00 /* PA<35:12> */
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#define IOPTE_C 0x00000080 /* cacheable */
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#define IOPTE_W 0x00000004 /* writeable */
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#define IOPTE_V 0x00000002 /* valid */
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#define IOPTE_WAZ 0x00000001 /* must write as zero */
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#define IOPTE_PPNSHFT 8 /* shift to get ppn from IOPTE */
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#define IOPTE_PPNPASHFT 4 /* shift to get pa from ioppn */
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#define IOPTE_BITS "\20\10C\3W\2V\1WAZ"
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