669 lines
22 KiB
C
669 lines
22 KiB
C
/*
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Van Jacobson of Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)scsireg.h 7.3 (Berkeley) 2/5/91
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*/
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/*
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* NCR 53C710 SCSI interface hardware description.
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*
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*/
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typedef struct {
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volatile unsigned char siop_sien; /* rw: SCSI Interrupt Enable */
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volatile unsigned char siop_sdid; /* rw: SCSI Destination ID */
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volatile unsigned char siop_scntl1; /* rw: SCSI control reg 1 */
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volatile unsigned char siop_scntl0; /* rw: SCSI control reg 0 */
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volatile unsigned char siop_socl; /* rw: SCSI Output Control Latch */
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volatile unsigned char siop_sodl; /* rw: SCSI Output Data Latch */
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volatile unsigned char siop_sxfer; /* rw: SCSI Transfer reg */
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volatile unsigned char siop_scid; /* rw: SCSI Chip ID reg */
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volatile unsigned char siop_sbcl; /* ro: SCSI Bus Control Lines */
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volatile unsigned char siop_sbdl; /* ro: SCSI Bus Data Lines */
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volatile unsigned char siop_sidl; /* ro: SCSI Input Data Latch */
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volatile unsigned char siop_sfbr; /* ro: SCSI First Byte Received */
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volatile unsigned char siop_sstat2; /* ro: SCSI status reg 2 */
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volatile unsigned char siop_sstat1; /* ro: SCSI status reg 1 */
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volatile unsigned char siop_sstat0; /* ro: SCSI status reg 0 */
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volatile unsigned char siop_dstat; /* ro: DMA status */
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volatile unsigned long siop_dsa; /* rw: Data Structure Address */
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volatile unsigned char siop_ctest3; /* ro: Chip test register 3 */
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volatile unsigned char siop_ctest2; /* ro: Chip test register 2 */
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volatile unsigned char siop_ctest1; /* ro: Chip test register 1 */
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volatile unsigned char siop_ctest0; /* ro: Chip test register 0 */
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volatile unsigned char siop_ctest7; /* rw: Chip test register 7 */
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volatile unsigned char siop_ctest6; /* rw: Chip test register 6 */
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volatile unsigned char siop_ctest5; /* rw: Chip test register 5 */
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volatile unsigned char siop_ctest4; /* rw: Chip test register 4 */
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volatile unsigned long siop_temp; /* rw: Temporary Stack reg */
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volatile unsigned char siop_lcrc; /* rw: LCRC value */
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volatile unsigned char siop_ctest8; /* rw: Chip test register 8 */
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volatile unsigned char siop_istat; /* rw: Interrupt Status reg */
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volatile unsigned char siop_dfifo; /* rw: DMA FIFO */
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volatile unsigned char siop_dcmd; /* rw: DMA Command Register */
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volatile unsigned char siop_dbc2; /* rw: DMA Byte Counter reg */
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volatile unsigned char siop_dbc1;
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volatile unsigned char siop_dbc0;
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volatile unsigned long siop_dnad; /* rw: DMA Next Address */
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volatile unsigned long siop_dsp; /* rw: DMA SCRIPTS Pointer reg */
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volatile unsigned long siop_dsps; /* rw: DMA SCRIPTS Pointer Save reg */
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volatile unsigned long siop_scratch; /* rw: Scratch Register */
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volatile unsigned char siop_dcntl; /* rw: DMA Control reg */
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volatile unsigned char siop_dwt; /* rw: DMA Watchdog Timer */
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volatile unsigned char siop_dien; /* rw: DMA Interrupt Enable */
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volatile unsigned char siop_dmode; /* rw: DMA Mode reg */
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volatile unsigned long siop_addr;
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} siop_regmap_t;
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/*
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* Register defines
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*/
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/* Scsi control register 0 (scntl0) */
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#define SIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */
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# define SIOP_ARB_SIMPLE 0x00
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# define SIOP_ARB_FULL 0xc0
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#define SIOP_SCNTL0_START 0x20 /* Start Sequence */
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#define SIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */
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#define SIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */
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#define SIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */
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#define SIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */
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#define SIOP_SCNTL0_TRG 0x01 /* Target Mode */
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/* Scsi control register 1 (scntl1) */
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#define SIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */
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#define SIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */
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#define SIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */
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#define SIOP_SCNTL1_CON 0x10 /* Connected */
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#define SIOP_SCNTL1_RST 0x08 /* Assert RST */
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#define SIOP_SCNTL1_PAR 0x04 /* Force bad Parity */
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#define SIOP_SCNTL1_SND 0x02 /* Start Send operation */
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#define SIOP_SCNTL1_RCV 0x01 /* Start Receive operation */
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/* Scsi interrupt enable register (sien) */
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#define SIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */
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#define SIOP_SIEN_FC 0x40 /* Function Complete */
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#define SIOP_SIEN_STO 0x20 /* (Re)Selection timeout */
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#define SIOP_SIEN_SEL 0x10 /* (Re)Selected */
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#define SIOP_SIEN_SGE 0x08 /* SCSI Gross Error */
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#define SIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */
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#define SIOP_SIEN_RST 0x02 /* RST asserted */
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#define SIOP_SIEN_PAR 0x01 /* Parity Error */
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/* Scsi chip ID (scid) */
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#define SIOP_SCID_VALUE(i) (1<<i)
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/* Scsi transfer register (sxfer) */
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#define SIOP_SXFER_DHP 0x80 /* Disable Halt on Parity error/ ATN asserted */
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#define SIOP_SXFER_TP 0x70 /* Synch Transfer Period */
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/* see specs for formulas:
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Period = TCP * (4 + XFERP )
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TCP = 1 + CLK + 1..2;
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*/
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#define SIOP_SXFER_MO 0x0f /* Synch Max Offset */
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# define SIOP_MAX_OFFSET 8
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/* Scsi output data latch register (sodl) */
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/* Scsi output control latch register (socl) */
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#define SIOP_REQ 0x80 /* SCSI signal <x> asserted */
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#define SIOP_ACK 0x40
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#define SIOP_BSY 0x20
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#define SIOP_SEL 0x10
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#define SIOP_ATN 0x08
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#define SIOP_MSG 0x04
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#define SIOP_CD 0x02
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#define SIOP_IO 0x01
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#define SIOP_PHASE(socl) SCSI_PHASE(socl)
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/* Scsi first byte received register (sfbr) */
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/* Scsi input data latch register (sidl) */
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/* Scsi bus data lines register (sbdl) */
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/* Scsi bus control lines register (sbcl). Same as socl */
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/* DMA status register (dstat) */
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#define SIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */
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#define SIOP_DSTAT_RES 0x60
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#define SIOP_DSTAT_ABRT 0x10 /* Aborted */
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#define SIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */
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#define SIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */
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#define SIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */
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#define SIOP_DSTAT_OPC 0x01 /* Invalid SCRIPTS Opcode */
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/* Scsi status register 0 (sstat0) */
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#define SIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */
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#define SIOP_SSTAT0_FC 0x40 /* Function Complete */
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#define SIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */
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#define SIOP_SSTAT0_SEL 0x10 /* (Re)Selected */
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#define SIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */
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#define SIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */
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#define SIOP_SSTAT0_RST 0x02 /* RST asserted */
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#define SIOP_SSTAT0_PAR 0x01 /* Parity Error */
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/* Scsi status register 1 (sstat1) */
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#define SIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */
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#define SIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */
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#define SIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */
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#define SIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */
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#define SIOP_SSTAT1_LOA 0x08 /* Lost arbitration */
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#define SIOP_SSTAT1_WOA 0x04 /* Won arbitration */
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#define SIOP_SSTAT1_RST 0x02 /* SCSI RST current value */
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#define SIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */
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/* Scsi status register 2 (sstat2) */
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#define SIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */
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# define SIOP_SCSI_FIFO_DEEP 8
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#define SIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */
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#define SIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */
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#define SIOP_SSTAT2_CD 0x02
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#define SIOP_SSTAT2_IO 0x01
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/* Chip test register 0 (ctest0) */
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#define SIOP_CTEST0_RES 0xfc
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#define SIOP_CTEST0_RTRG 0x02 /* Real Target mode */
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#define SIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */
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/* Chip test register 1 (ctest1) */
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#define SIOP_CTEST1_FMT 0xf0 /* Byte empty in DMA FIFO bottom (high->byte3) */
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#define SIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */
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/* Chip test register 2 (ctest2) */
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#define SIOP_CTEST2_RES 0xc0
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#define SIOP_CTEST2_SOFF 0x20 /* Synch Offset compare (1-> zero Init, max Tgt */
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#define SIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */
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#define SIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */
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#define SIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */
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#define SIOP_CTEST2_DREQ 0x02 /* DREQ status */
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#define SIOP_CTEST2_DACK 0x01 /* DACK status */
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/* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */
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/* Chip test register 4 (ctest4) */
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#define SIOP_CTEST4_RES 0x80
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#define SIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */
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#define SIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */
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#define SIOP_CTEST4_SLBE 0x10 /* SCSI loobpack enable */
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#define SIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */
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#define SIOP_CTEST4_FBL 0x07 /* DMA FIFO Byte Lane select (from ctest6)
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4->0, .. 7->3 */
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/* Chip test register 5 (ctest5) */
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#define SIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */
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#define SIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */
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#define SIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */
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#define SIOP_CTEST5_MASR 0x10 /* Master set/reset pulses (of bits 3-0) */
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#define SIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */
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#define SIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */
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#define SIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */
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#define SIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */
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/* Chip test register 6 (ctest6) DMA FIFO access */
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/* Chip test register 7 (ctest7) */
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#define SIOP_CTEST7_RES 0xe0
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#define SIOP_CTEST7_STD 0x10 /* Disable selection timeout */
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#define SIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */
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#define SIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */
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#define SIOP_CTEST7_DC 0x02 /* Drive DC pin low on SCRIPT fetches */
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#define SIOP_CTEST7_DIFF 0x01 /* Differential mode */
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/* DMA FIFO register (dfifo) */
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#define SIOP_DFIFO_FLF 0x80 /* Flush (spill) DMA FIFO */
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#define SIOP_DFIFO_CLF 0x40 /* Clear DMA and SCSI FIFOs */
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#define SIOP_DFIFO_BO 0x3f /* FIFO byte offset counter */
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/* Interrupt status register (istat) */
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#define SIOP_ISTAT_ABRT 0x80 /* Abort operation */
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#define SIOP_ISTAT_RES 0x70
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#define SIOP_ISTAT_CON 0x08 /* Connected */
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#define SIOP_ISTAT_PRE 0x04 /* Pointer register empty */
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#define SIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */
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#define SIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */
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/* DMA Mode register (dmode) */
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#define SIOP_DMODE_BL_MASK 0xc0 /* 0->1 1->2 2->4 3->8 */
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#define SIOP_DMODE_BW16 0x20 /* Bus Width is 16 bits */
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#define SIOP_DMODE_286 0x10 /* 286 mode */
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#define SIOP_DMODE_IO_M 0x08 /* xfer data to memory or I/O space */
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#define SIOP_DMODE_FAM 0x04 /* fixed address mode */
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#define SIOP_DMODE_PIPE 0x02 /* SCRIPTS in Pipeline mode */
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#define SIOP_DMODE_MAN 0x01 /* SCRIPTS in Manual start mode */
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/* DMA interrupt enable register (dien) */
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#define SIOP_DIEN_RES 0xe0
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#define SIOP_DIEN_ABRT 0x10 /* On Abort */
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#define SIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */
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#define SIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */
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#define SIOP_DIEN_WTD 0x02 /* On watchdog timeout */
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#define SIOP_DIEN_OPC 0x01 /* On SCRIPTS illegal opcode */
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/* DMA control register (dcntl) */
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#define SIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers:
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0 --> 37.51..50.00 Mhz, div=2
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1 --> 25.01..37.50 Mhz, div=1.5
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2 --> 16.67..25.00 Mhz, div=1
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3 --> reserved
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*/
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#define SIOP_DCNTL_S16 0x20 /* SCRIPTS fetches 16bits at a time */
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#define SIOP_DCNTL_SSM 0x10 /* Single step mode */
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#define SIOP_DCNTL_LLM 0x08 /* Enable Low-level mode */
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#define SIOP_DCNTL_STD 0x04 /* Start SCRIPTS operation */
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#define SIOP_DCNTL_RES 0x02
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#define SIOP_DCNTL_RST 0x01 /* Software reset */
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/* psns/pctl phase lines as bits */
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#define PHASE_MSG 0x04
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#define PHASE_CD 0x02 /* =1 if 'command' */
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#define PHASE_IO 0x01 /* =1 if data inbound */
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/* Phase lines as values */
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#define PHASE 0x07 /* mask for psns/pctl phase */
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#define DATA_OUT_PHASE 0x00
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#define DATA_IN_PHASE 0x01
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#define CMD_PHASE 0x02
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#define STATUS_PHASE 0x03
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#define BUS_FREE_PHASE 0x04
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#define ARB_SEL_PHASE 0x05 /* Fuji chip combines arbitration with sel. */
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#define MESG_OUT_PHASE 0x06
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#define MESG_IN_PHASE 0x07
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/* SCSI Messages */
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#define MSG_CMD_COMPLETE 0x00
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#define MSG_EXT_MESSAGE 0x01
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#define MSG_SAVE_DATA_PTR 0x02
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#define MSG_RESTORE_PTR 0x03
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#define MSG_DISCONNECT 0x04
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#define MSG_INIT_DETECT_ERROR 0x05
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#define MSG_ABORT 0x06
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#define MSG_REJECT 0x07
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#define MSG_NOOP 0x08
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#define MSG_PARITY_ERROR 0x09
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#define MSG_BUS_DEVICE_RESET 0x0C
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#define MSG_IDENTIFY 0x80
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#define MSG_IDENTIFY_DR 0xc0 /* (disconnect/reconnect allowed) */
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#define MSG_SYNC_REQ 0x01
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/* SCSI Commands */
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#define CMD_TEST_UNIT_READY 0x00
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#define CMD_REQUEST_SENSE 0x03
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#define CMD_INQUIRY 0x12
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#define CMD_SEND_DIAGNOSTIC 0x1D
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#define CMD_REWIND 0x01
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#define CMD_FORMAT_UNIT 0x04
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#define CMD_READ_BLOCK_LIMITS 0x05
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#define CMD_REASSIGN_BLOCKS 0x07
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#define CMD_READ 0x08
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#define CMD_WRITE 0x0A
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#define CMD_WRITE_FILEMARK 0x10
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#define CMD_SPACE 0x11
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#define CMD_MODE_SELECT 0x15
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#define CMD_RELEASE_UNIT 0x17
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#define CMD_ERASE 0x19
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#define CMD_MODE_SENSE 0x1A
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#define CMD_LOADUNLOAD 0x1B
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#define CMD_RECEIVE_DIAG 0x1C
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#define CMD_SEND_DIAG 0x1D
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#define CMD_P_A_MEDIA_REMOVAL 0x1E
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#define CMD_READ_CAPACITY 0x25
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#define CMD_READ_EXT 0x28
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#define CMD_WRITE_EXT 0x2A
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#define CMD_READ_DEFECT_DATA 0x37
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#define SD_MANUFAC_DEFECTS 0x14000000
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#define SD_GROWN_DEFECTS 0x0c000000
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#define CMD_READ_BUFFER 0x3B
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#define CMD_WRITE_BUFFER 0x3C
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#define CMD_READ_FULL 0xF0
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#define CMD_MEDIA_TEST 0xF1
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#define CMD_ACCESS_LOG 0xF2
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#define CMD_WRITE_FULL 0xFC
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#define CMD_MANAGE_PRIMARY 0xFD
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#define CMD_EXECUTE_DATA 0xFE
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/* SCSI status bits */
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#define STS_CHECKCOND 0x02 /* Check Condition (ie., read sense) */
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#define STS_CONDMET 0x04 /* Condition Met (ie., search worked) */
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#define STS_BUSY 0x08
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#define STS_INTERMED 0x10 /* Intermediate status sent */
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#define STS_EXT 0x80 /* Extended status valid */
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/* command descriptor blocks */
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struct scsi_cdb6 {
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u_char cmd; /* command code */
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u_char lun: 3, /* logical unit on ctlr */
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lbah: 5; /* msb of read/write logical block addr */
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u_char lbam; /* middle byte of l.b.a. */
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u_char lbal; /* lsb of l.b.a. */
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u_char len; /* transfer length */
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u_char xtra;
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};
|
|
|
|
struct scsi_cdb10 {
|
|
u_char cmd; /* command code */
|
|
u_char lun: 3, /* logical unit on ctlr */
|
|
: 4,
|
|
rel: 1; /* l.b.a. is relative addr if =1 */
|
|
u_char lbah; /* msb of read/write logical block addr */
|
|
u_char lbahm; /* high middle byte of l.b.a. */
|
|
u_char lbalm; /* low middle byte of l.b.a. */
|
|
u_char lbal; /* lsb of l.b.a. */
|
|
u_char reserved;
|
|
u_char lenh; /* msb transfer length */
|
|
u_char lenl; /* lsb transfer length */
|
|
u_char xtra;
|
|
};
|
|
|
|
/* basic sense data */
|
|
|
|
struct scsi_sense {
|
|
u_char valid: 1, /* l.b.a. is valid */
|
|
class: 3,
|
|
code: 4;
|
|
u_char vu: 4, /* vendor unique */
|
|
lbah: 4;
|
|
u_char lbam;
|
|
u_char lbal;
|
|
};
|
|
|
|
struct scsi_xsense {
|
|
u_char valid: 1, /* l.b.a. is valid */
|
|
class: 3,
|
|
code: 4;
|
|
u_char segment;
|
|
u_char filemark: 1,
|
|
eom: 1,
|
|
ili: 1, /* illegal length indicator */
|
|
rsvd: 1,
|
|
key: 4;
|
|
u_char info1;
|
|
u_char info2;
|
|
u_char info3;
|
|
u_char info4;
|
|
u_char len; /* additional sense length */
|
|
};
|
|
|
|
/* inquiry data */
|
|
struct scsi_inquiry {
|
|
u_char type;
|
|
u_char qual;
|
|
u_char version;
|
|
u_char rsvd;
|
|
u_char len;
|
|
char class[3];
|
|
char vendor_id[8];
|
|
char product_id[16];
|
|
char rev[4];
|
|
};
|
|
|
|
struct scsi_format_parms { /* physical BFI format */
|
|
u_short reserved;
|
|
u_short list_len;
|
|
struct defect {
|
|
unsigned cyl : 24;
|
|
unsigned head : 8;
|
|
long bytes_from_index;
|
|
} defect[127];
|
|
} format_parms;
|
|
|
|
struct scsi_reassign_parms {
|
|
u_short reserved;
|
|
u_short list_len; /* length in bytes of defects only */
|
|
struct new_defect {
|
|
unsigned lba; /* logical block address */
|
|
} new_defect[2];
|
|
} reassign_parms;
|
|
|
|
struct scsi_modesel_hdr {
|
|
u_char rsvd1;
|
|
u_char media_type;
|
|
u_char rsvd2;
|
|
u_char block_desc_len;
|
|
u_int density : 8;
|
|
u_int number_blocks :24;
|
|
u_int rsvd3 : 8;
|
|
u_int block_length :24;
|
|
};
|
|
|
|
struct scsi_modesense_hdr {
|
|
u_char len;
|
|
u_char media_type;
|
|
u_char wp : 1;
|
|
u_char rsvd1 : 7;
|
|
u_char block_desc_len;
|
|
u_int density : 8;
|
|
u_int number_blocks :24;
|
|
u_int rsvd2 : 8;
|
|
u_int block_length :24;
|
|
};
|
|
|
|
/*
|
|
* Mode Select / Mode sense "pages"
|
|
*/
|
|
|
|
/*
|
|
* Page One - Error Recovery Parameters
|
|
*/
|
|
struct scsi_err_recovery {
|
|
u_char page_savable : 1; /* save parameters */
|
|
u_char reserved : 1;
|
|
u_char page_code : 6; /* = 0x01 */
|
|
u_char page_length; /* = 6 */
|
|
u_char awre : 1; /* auto write realloc enabled */
|
|
u_char arre : 1; /* auto read realloc enabled */
|
|
u_char tb : 1; /* transfer block */
|
|
u_char rc : 1; /* read continuous */
|
|
u_char eec : 1; /* enable early correction */
|
|
u_char per : 1; /* post error */
|
|
u_char dte : 1; /* disable transfer on error */
|
|
u_char dcr : 1; /* disable correction */
|
|
u_char retry_count;
|
|
u_char correction_span;
|
|
u_char head_offset_count;
|
|
u_char strobe_offset_count;
|
|
u_char recovery_time_limit;
|
|
};
|
|
|
|
/*
|
|
* Page Two - Disconnect / Reconnect Control Parameters
|
|
*/
|
|
struct scsi_disco_reco {
|
|
u_char page_savable : 1; /* save parameters */
|
|
u_char rsvd : 1;
|
|
u_char page_code : 6; /* = 0x02 */
|
|
u_char page_length; /* = 10 */
|
|
u_char buffer_full_ratio; /* write, how full before reconnect? */
|
|
u_char buffer_empty_ratio; /* read, how full before reconnect? */
|
|
|
|
u_short bus_inactivity_limit; /* how much bus time for busy */
|
|
u_short disconnect_time_limit; /* min to remain disconnected */
|
|
u_short connect_time_limit; /* min to remain connected */
|
|
u_short reserved_1;
|
|
};
|
|
|
|
/*
|
|
* Page Three - Direct Access Device Format Parameters
|
|
*/
|
|
struct scsi_format {
|
|
u_char page_savable : 1; /* save parameters */
|
|
u_char rsvd : 1;
|
|
u_char page_code : 6; /* = 0x03 */
|
|
u_char page_length; /* = 22 */
|
|
u_short tracks_per_zone; /* Handling of Defects Fields */
|
|
u_short alt_sect_zone;
|
|
u_short alt_tracks_zone;
|
|
u_short alt_tracks_vol;
|
|
u_short sect_track; /* Track Format Field */
|
|
u_short data_sect; /* Sector Format Fields */
|
|
u_short interleave;
|
|
u_short track_skew_factor;
|
|
u_short cyl_skew_factor;
|
|
u_char ssec : 1; /* Drive Type Field */
|
|
u_char hsec : 1;
|
|
u_char rmb : 1;
|
|
u_char surf : 1;
|
|
u_char ins : 1;
|
|
u_char reserved_1 : 3;
|
|
u_char reserved_2;
|
|
u_char reserved_3;
|
|
u_char reserved_4;
|
|
};
|
|
|
|
/*
|
|
* Page Four - Rigid Disk Drive Geometry Parameters
|
|
*/
|
|
struct scsi_geometry {
|
|
u_char page_savable : 1; /* save parameters */
|
|
u_char rsvd : 1;
|
|
u_char page_code : 6; /* = 0x04 */
|
|
u_char page_length; /* = 18 */
|
|
u_char cyl_ub; /* number of cylinders */
|
|
u_char cyl_mb;
|
|
u_char cyl_lb;
|
|
u_char heads; /* number of heads */
|
|
u_char precomp_cyl_ub; /* cylinder to start precomp */
|
|
u_char precomp_cyl_mb;
|
|
u_char precomp_cyl_lb;
|
|
u_char current_cyl_ub; /* cyl to start reduced current */
|
|
u_char current_cyl_mb;
|
|
u_char current_cyl_lb;
|
|
u_short step_rate; /* drive step rate */
|
|
u_char landing_cyl_ub; /* landing zone cylinder */
|
|
u_char landing_cyl_mb;
|
|
u_char landing_cyl_lb;
|
|
u_char reserved_1;
|
|
u_char reserved_2;
|
|
u_char reserved_3;
|
|
};
|
|
|
|
/*
|
|
* Page 0x38 - Cache Control Parameters
|
|
*/
|
|
struct scsi_cache {
|
|
u_char page_savable : 1; /* save parameters */
|
|
u_char rsvd : 1;
|
|
u_char page_code : 6; /* = 0x38 */
|
|
u_char page_length; /* = 14 */
|
|
u_char rsvd_1 : 1;
|
|
u_char wie : 1; /* write index enable */
|
|
u_char rsvd_2 : 1;
|
|
u_char ce : 1; /* cache enable */
|
|
u_char table_size : 4;
|
|
u_char prefetch_threshold;
|
|
u_char maximum_threshold;
|
|
u_char maximumprefetch_multiplier;
|
|
u_char minimum_threshold;
|
|
u_char minimum_prefetch_multiplier;
|
|
u_char reserved[8];
|
|
};
|
|
|
|
/*
|
|
* Driver ioctl's for various scsi operations.
|
|
*/
|
|
#ifndef _IOCTL_
|
|
#include "ioctl.h"
|
|
#endif
|
|
|
|
/*
|
|
* Control for SCSI "format" mode.
|
|
*
|
|
* "Format" mode allows a privileged process to issue direct SCSI
|
|
* commands to a drive (it is intended primarily to allow on-line
|
|
* formatting). SDIOCSFORMAT with a non-zero arg will put the drive
|
|
* into format mode; a zero arg will take it out. When in format
|
|
* mode, only the process that issued the SDIOCFORMAT can read or
|
|
* write the drive.
|
|
*
|
|
* In format mode, process is expected to
|
|
* - do SDIOCSCSICOMMAND to supply cdb for next SCSI op
|
|
* - do read or write as appropriate for cdb
|
|
* - if i/o error, optionally do SDIOCSENSE to get completion
|
|
* status and sense data from last scsi operation.
|
|
*/
|
|
|
|
struct scsi_fmt_cdb {
|
|
int len; /* cdb length (in bytes) */
|
|
u_char cdb[28]; /* cdb to use on next read/write */
|
|
};
|
|
|
|
struct scsi_fmt_sense {
|
|
u_int status; /* completion status of last op */
|
|
u_char sense[28]; /* sense data (if any) from last op */
|
|
};
|
|
|
|
#define SDIOCSFORMAT _IOW('S', 0x1, int)
|
|
#define SDIOCGFORMAT _IOR('S', 0x2, int)
|
|
#define SDIOCSCSICOMMAND _IOW('S', 0x3, struct scsi_fmt_cdb)
|
|
#define SDIOCSENSE _IOR('S', 0x4, struct scsi_fmt_sense)
|
|
|
|
extern void siopreset (int unit);
|
|
extern void siopstart (int unit);
|
|
extern int siopgo (int ctlr, int slave, int unit, struct buf *bp, struct scsi_fmt_cdb *cdb, int pad);
|
|
extern void siopdone (int unit);
|
|
#if 0
|
|
extern int siopintr2 (int unit);
|
|
#else
|
|
extern int siopintr2 (void);
|
|
#endif
|