373 lines
11 KiB
C
373 lines
11 KiB
C
/* $NetBSD: gxpcic.c,v 1.2 2006/10/17 17:06:22 kiyohara Exp $ */
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/*
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* Copyright (C) 2005, 2006 WIDE Project and SOUM Corporation.
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* All rights reserved.
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*
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* Written by Takashi Kiyohara and Susumu Miki for WIDE Project and SOUM
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* Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the project nor the name of SOUM Corporation
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE PROJECT and SOUM CORPORATION ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE PROJECT AND SOUM CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 2002, 2003, 2005 Genetec corp. All rights reserved.
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*
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* PCMCIA/CF support for TWINTAIL (G4255EB)
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* Written by Hiroyuki Bessho for Genetec corp.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Genetec corp. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/callout.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/malloc.h>
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#include <uvm/uvm.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/pcmcia/pcmciareg.h>
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#include <dev/pcmcia/pcmciavar.h>
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#include <dev/pcmcia/pcmciachip.h>
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#include <arch/arm/xscale/pxa2x0var.h>
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#include <arch/arm/xscale/pxa2x0reg.h>
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#include <arch/arm/sa11x0/sa11xx_pcicvar.h>
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#include <arch/evbarm/gumstix/gumstixvar.h>
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#ifdef DEBUG
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#define DPRINTF(arg) printf arg
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#else
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#define DPRINTF(arg)
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#endif
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#define HAVE_CARD(r) (!((r) & GPIO_SET))
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#define GXIO_GPIO8_RESET 8
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#define GXIO_GPIRQ11_nCD 11
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#define GXIO_GPIO26_READY 26
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struct gxpcic_softc;
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struct gxpcic_socket {
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struct sapcic_socket ss; /* inherit socket for sa11x0 pcic */
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};
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struct gxpcic_softc {
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struct sapcic_softc sc_pc; /* inherit SA11xx pcic */
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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int sc_gpirq;
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struct gxpcic_socket sc_socket[2];
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int sc_cards;
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};
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static int gxpcic_match(struct device *, struct cfdata *, void *);
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static void gxpcic_attach(struct device *, struct device *, void *);
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static int gxpcic_card_detect(void *);
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static int gxpcic_read(struct sapcic_socket *, int);
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static void gxpcic_write(struct sapcic_socket *, int, int);
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static void gxpcic_set_power(struct sapcic_socket *, int);
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static void gxpcic_clear_intr(int);
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static void *gxpcic_intr_establish(struct sapcic_socket *, int,
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int (*)(void *), void *);
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static void gxpcic_intr_disestablish(struct sapcic_socket *, void *);
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CFATTACH_DECL(gxpcic, sizeof(struct gxpcic_softc),
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gxpcic_match, gxpcic_attach, NULL, NULL);
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static struct sapcic_tag gxpcic_tag = {
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gxpcic_read,
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gxpcic_write,
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gxpcic_set_power,
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gxpcic_clear_intr,
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gxpcic_intr_establish,
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gxpcic_intr_disestablish,
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};
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static int
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gxpcic_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct {
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int gpio;
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u_int fn;
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} gpiomodes[] = {
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{ 48, GPIO_ALT_FN_2_OUT }, /* nPOE */
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{ 49, GPIO_ALT_FN_2_OUT }, /* nPWE */
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{ 50, GPIO_ALT_FN_2_OUT }, /* nPIOR */
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{ 51, GPIO_ALT_FN_2_OUT }, /* nPIOW */
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{ 54, GPIO_ALT_FN_2_OUT }, /* pSKTSEL */
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{ 55, GPIO_ALT_FN_2_OUT }, /* nPREG */
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{ 56, GPIO_ALT_FN_1_IN }, /* nPWAIT */
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{ 57, GPIO_ALT_FN_1_IN }, /* nIOIS16 */
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{ -1 }
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};
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u_int reg;
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int i;
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for (i = 0; gpiomodes[i].gpio != -1; i++) {
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reg = pxa2x0_gpio_get_function(gpiomodes[i].gpio);
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if (GPIO_FN(reg) != GPIO_FN(gpiomodes[i].fn) ||
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GPIO_FN_IS_OUT(reg) != GPIO_FN_IS_OUT(gpiomodes[i].fn))
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break;
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}
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if (gpiomodes[i].gpio != -1)
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return 0;
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return 1; /* match */
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}
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static void
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gxpcic_attach(struct device *parent, struct device *self, void *aux)
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{
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struct gxio_softc *gxsc = (struct gxio_softc *)parent;
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struct gxpcic_softc *sc = (struct gxpcic_softc *)self;
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struct gxio_attach_args *gxa = aux;
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struct pcmciabus_attach_args paa;
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int mecr, val, i, n;
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printf("\n");
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sc->sc_iot = sc->sc_pc.sc_iot = gxa->gxa_iot;
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sc->sc_ioh = gxsc->sc_ioh;
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sc->sc_gpirq = gxa->gxa_gpirq;
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sc->sc_cards = 0;
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n = bus_space_read_4(sc->sc_iot, sc->sc_ioh, MEMCTL_MECR) & MECR_NOS ?
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2 : 1;
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for (i = 0; i < n; i++) {
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sc->sc_socket[i].ss.sc = &sc->sc_pc;
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sc->sc_socket[i].ss.socket = 0;
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sc->sc_socket[i].ss.pcictag_cookie = NULL;
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sc->sc_socket[i].ss.pcictag = &gxpcic_tag;
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sc->sc_socket[i].ss.event_thread = NULL;
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sc->sc_socket[i].ss.event = 0;
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sc->sc_socket[i].ss.laststatus = SAPCIC_CARD_INVALID;
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sc->sc_socket[i].ss.shutdown = 0;
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/* 3.3V only? */
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sc->sc_socket[i].ss.power_capability = SAPCIC_POWER_3V;
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, MEMCTL_MCMEM(i),
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MC_TIMING_VAL(10,10,30));
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, MEMCTL_MCATT(i),
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MC_TIMING_VAL(10,10,30));
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, MEMCTL_MCIO(i),
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MC_TIMING_VAL(6,6,17));
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paa.paa_busname = "pcmcia";
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paa.pct = (pcmcia_chipset_tag_t)&sa11x0_pcmcia_functions;
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paa.pch = (pcmcia_chipset_handle_t)&sc->sc_socket[i].ss;
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paa.iobase = 0;
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paa.iosize = 0x4000000;
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sc->sc_socket[i].ss.pcmcia =
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(struct device *)config_found_ia(&sc->sc_pc.sc_dev,
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"pcmciabus", &paa, NULL);
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/* interrupt for card insertion/removal */
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gxio_intr_establish(sc, GXIO_GPIRQ11_nCD, IST_EDGE_BOTH,
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IPL_BIO, gxpcic_card_detect, &sc->sc_socket[i]);
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/* if card was insert then set CIT */
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val = pxa2x0_gpio_get_function(GXIO_GPIRQ11_nCD);
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if (HAVE_CARD(val)) {
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mecr = bus_space_read_4(
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sc->sc_iot, sc->sc_ioh, MEMCTL_MECR);
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bus_space_write_4(sc->sc_iot,
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sc->sc_ioh, MEMCTL_MECR, mecr | MECR_CIT);
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}
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/* schedule kthread creation */
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kthread_create(sapcic_kthread_create, &sc->sc_socket[i].ss);
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}
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}
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static int
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gxpcic_card_detect(void *arg)
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{
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struct gxpcic_socket *socket = arg;
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struct gxpcic_softc *sc = (struct gxpcic_softc *)socket->ss.sc;
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int sock_no = socket->ss.socket;
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int mecr, last, val, s;
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s = splbio();
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last = sc->sc_cards;
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val = pxa2x0_gpio_get_function(GXIO_GPIRQ11_nCD);
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if (HAVE_CARD(val)) {
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sc->sc_cards |= 1<<sock_no;
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/* if it is the first card, turn on expansion memory control. */
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if (last == 0) {
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mecr = bus_space_read_4(
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sc->sc_iot, sc->sc_ioh, MEMCTL_MECR);
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bus_space_write_4(sc->sc_iot,
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sc->sc_ioh, MEMCTL_MECR, mecr | MECR_CIT);
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}
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} else {
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sc->sc_cards &= ~(1<<sock_no);
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/* if we loast all cards, turn off expansion memory control. */
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if (sc->sc_cards == 0) {
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mecr = bus_space_read_4(
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sc->sc_iot, sc->sc_ioh, MEMCTL_MECR);
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bus_space_write_4(sc->sc_iot,
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sc->sc_ioh, MEMCTL_MECR, mecr & ~MECR_CIT);
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}
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}
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splx(s);
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DPRINTF(("%s: card %d %s\n", sc->sc_pc.sc_dev.dv_xname, sock_no,
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HAVE_CARD(val) ? "inserted" : "removed"));
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sapcic_intr(arg);
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return 1;
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}
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/* ARGSUSED */
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static int
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gxpcic_read(struct sapcic_socket *so, int which)
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{
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int reg;
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switch (which) {
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case SAPCIC_STATUS_CARD:
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reg = pxa2x0_gpio_get_function(GXIO_GPIRQ11_nCD);
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return (HAVE_CARD(reg) ?
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SAPCIC_CARD_VALID : SAPCIC_CARD_INVALID);
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case SAPCIC_STATUS_READY:
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reg = pxa2x0_gpio_get_function(GXIO_GPIO26_READY);
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return (reg & GPIO_SET ? 1 : 0);
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default:
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panic("%s: bogus register", __FUNCTION__);
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}
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}
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/* ARGSUSED */
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static void
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gxpcic_write(struct sapcic_socket *so, int which, int arg)
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{
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switch (which) {
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case SAPCIC_CONTROL_RESET:
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#if 0 /* XXXX: Our PXA2x0 no necessary ??? */
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if (arg)
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pxa2x0_gpio_set_function(GXIO_GPIO8_RESET, GPIO_SET);
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else
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pxa2x0_gpio_set_function(GXIO_GPIO8_RESET, GPIO_CLR);
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#endif
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break;
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case SAPCIC_CONTROL_LINEENABLE:
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break;
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case SAPCIC_CONTROL_WAITENABLE:
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break;
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case SAPCIC_CONTROL_POWERSELECT:
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break;
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default:
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panic("%s: bogus register", __FUNCTION__);
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}
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}
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static void
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gxpcic_set_power(struct sapcic_socket *__so, int arg)
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{
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if(arg != SAPCIC_POWER_OFF && arg != SAPCIC_POWER_3V)
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panic("%s: bogus arg\n", __FUNCTION__);
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/* 3.3V only? */
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}
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/* ARGSUSED */
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static void
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gxpcic_clear_intr(int arg)
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{
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/* nothing to do */
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}
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static void *
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gxpcic_intr_establish(struct sapcic_socket *so, int level,
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int (* ih_fun)(void *), void *ih_arg)
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{
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__attribute__((unused))struct gxpcic_softc *sc =
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(struct gxpcic_softc *)so->sc;
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int gpirq;
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gpirq = GXIO_GPIO26_READY;
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DPRINTF(("%s: card %d gpio %d\n",
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sc->sc_pc.sc_dev.dv_xname, so->socket, gpirq));
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return gxio_intr_establish(sc, gpirq, IST_EDGE_FALLING, level,
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ih_fun, ih_arg);
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}
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static void
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gxpcic_intr_disestablish(struct sapcic_socket *so, void *ih)
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{
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__attribute__((unused))struct gxpcic_softc *sc =
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(struct gxpcic_softc *)so->sc;
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gxio_intr_disestablish(sc, ih);
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}
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