425 lines
12 KiB
C
425 lines
12 KiB
C
/* $NetBSD: igsfbreg.h,v 1.3 2002/09/24 18:17:25 uwe Exp $ */
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/*
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* Copyright (c) 2002 Valeriy E. Ushakov
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Integraphics Systems IGA 168x and CyberPro series.
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* Only tested on IGA 1682 in Krups JavaStation-NC.
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*/
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#ifndef _DEV_IC_IGSFBREG_H_
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#define _DEV_IC_IGSFBREG_H_
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/*
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* Magic address decoding for memory space accesses in CyberPro.
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*/
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#define IGS_MEM_MMIO_SELECT 0x00800000 /* memory mapped i/o */
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#define IGS_MEM_BE_SELECT 0x00400000 /* endian select */
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/*
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* Cursor sprite data in linear memory at IGS_EXT_SPRITE_DATA_{LO,HI}.
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* 64x64 pixels, 2bpp = 1Kb
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*/
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#define IGS_CURSOR_DATA_SIZE 1024
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/*
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* Starting up the chip.
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*/
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/* Video Enable/Setup */
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#define IGS_VDO 0x46e8
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#define IGS_VDO_ENABLE 0x08
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#define IGS_VDO_SETUP 0x10
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/* Video Enable */
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#define IGS_VSE 0x102
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#define IGS_VSE_ENABLE 0x01
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/*
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* We map only 32 bytes of actual IGS registers at 0x3c0..0x3df.
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* This macro helps to define register names using their "absolute"
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* locations - it makes matching defines against docs easier.
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*/
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#define IGS_REG_BASE 0x3c0
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#define IGS_REG_SIZE 0x020
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#define IGS_REG_(x) ((x) - IGS_REG_BASE)
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/*
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* Attribute controller. Flip-flop reset by IGS_INPUT_STATUS1 at 0x3da.
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* We don't bother defining actual registers, we only use them once
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* during video initialization.
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*/
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#define IGS_ATTR_IDX IGS_REG_(0x3c0)
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#define IGS_ATTR_PORT IGS_REG_(0x3c1)
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/*
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* Misc output register. We only use the _W register during video
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* initialization.
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*/
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#define IGS_MISC_OUTPUT_W IGS_REG_(0x3c2)
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#define IGS_MISC_OUTPUT_R IGS_REG_(0x3cc)
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/*
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* SEQUENCER.
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*/
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#define IGS_SEQ_IDX IGS_REG_(0x3c4)
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#define IGS_SEQ_PORT IGS_REG_(0x3c5)
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#define IGS_SEQ_RESET 0x0
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#define IGS_SEQ_RESET_ASYNC 0x01
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#define IGS_SEQ_RESET_SYNC 0x02
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/* IGS_EXT_SPRITE_CTL/IGS_EXT_SPRITE_DAC_PEL (3cf/56[2]) == 0 */
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#define IGS_PEL_MASK IGS_REG_(0x3c6)
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/* IGS_EXT_SPRITE_CTL/IGS_EXT_SPRITE_DAC_PEL 3cf/56[2] == 1 */
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#define IGS_DAC_CMD IGS_REG_(0x3c6)
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/*
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* Palette Read/Write: write palette index to the index port.
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* Read/write R/G/B in three consecutive accesses to data port.
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* After third access to data the index is autoincremented and you can
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* proceed with reading/writing data port for the next entry.
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*
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* When IGS_EXT_SPRITE_DAC_PEL bit in sprite control is set, these
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* registers are used to access sprite (i.e. cursor) 2-color palette.
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* (NB: apparently, in this mode index autoincrement doesn't work).
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*/
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#define IGS_DAC_PEL_READ_IDX IGS_REG_(0x3c7)
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#define IGS_DAC_PEL_WRITE_IDX IGS_REG_(0x3c8)
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#define IGS_DAC_PEL_DATA IGS_REG_(0x3c9)
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/*
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* GRAPHICS CONTROLLER registers.
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*/
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#define IGS_GRFX_IDX IGS_REG_(0x3ce)
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#define IGS_GRFX_PORT IGS_REG_(0x3cf)
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/*
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* EXTENDED registers.
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*/
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#define IGS_EXT_IDX IGS_REG_(0x3ce)
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#define IGS_EXT_PORT IGS_REG_(0x3cf)
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/* [3..0] -> [19..16] of start addr if IGS_EXT_START_ADDR_ON is set */
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#define IGS_EXT_START_ADDR 0x10
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#define IGS_EXT_START_ADDR_ON 0x10
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/* overflow 10th bits for severl crtc registers; interlaced mode select */
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#define IGS_EXT_VOVFL 0x11
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#define IGS_EXT_VOVFL_INTERLACED 0x20
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#define IGS_EXT_IRQ_CTL 0x12
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#define IGS_EXT_IRQ_ENABLE 0x01
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/*
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* Sync Control.
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* Two-bit combinations for h/v:
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* 00 - normal, 01 - force 0, 1x - force 1
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*/
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#define IGS_EXT_SYNC_CTL 0x16
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#define IGS_EXT_SYNC_H0 0x01
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#define IGS_EXT_SYNC_H1 0x02
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#define IGS_EXT_SYNC_V0 0x04
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#define IGS_EXT_SYNC_V1 0x08
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/*
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* For PCI just use normal BAR config.
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*/
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#define IGS_EXT_BUS_CTL 0x30
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#define IGS_EXT_BUS_CTL_LINSIZE_SHIFT 0
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#define IGS_EXT_BUS_CTL_LINSIZE_MASK 0x03
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#define IGS_EXT_BUS_CTL_LINSIZE(x) \
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(((x) >> IGS_EXT_BUS_CTL_LINSIZE_SHIFT) & IGS_EXT_BUS_CTL_LINSIZE_MASK)
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/*
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* COPREN - enable direct access to coprocessor registers
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* COPASELB - select IGS_COP_BASE_B for COP address
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*/
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#define IGS_EXT_BIU_MISC_CTL 0x33
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#define IGS_EXT_BIU_LINEAREN 0x01
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#define IGS_EXT_BIU_LIN2MEM 0x02
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#define IGS_EXT_BIU_COPREN 0x04
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#define IGS_EXT_BIU_COPASELB 0x08
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#define IGS_EXT_BIU_SEGON 0x10
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#define IGS_EXT_BIU_SEG2MEM 0x20
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/*
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* Linear Address registers
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* PCI: don't write directly, just use nomral PCI configuration
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* ISA: only bits [23..20] are programmable, the rest MBZ
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*/
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#define IGS_EXT_LINA_LO 0x34 /* [3..0] -> [23..20] */
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#define IGS_EXT_LINA_HI 0x35 /* [7..0] -> [31..24] */
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/* Hardware cursor on-screen location and hot spot */
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#define IGS_EXT_SPRITE_HSTART_LO 0x50
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#define IGS_EXT_SPRITE_HSTART_HI 0x51 /* bits [2..0] */
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#define IGS_EXT_SPRITE_HPRESET 0x52 /* bits [5..0] */
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#define IGS_EXT_SPRITE_VSTART_LO 0x53
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#define IGS_EXT_SPRITE_VSTART_HI 0x54 /* bits [2..0] */
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#define IGS_EXT_SPRITE_VPRESET 0x55 /* bits [5..0] */
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/* Hardware cursor control */
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#define IGS_EXT_SPRITE_CTL 0x56
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#define IGS_EXT_SPRITE_VISIBLE 0x01
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#define IGS_EXT_SPRITE_64x64 0x02
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#define IGS_EXT_SPRITE_DAC_PEL 0x04
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/* bits unrelated to sprite control */
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#define IGS_EXT_COP_RESET 0x08
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/* Extended graphics mode */
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#define IGS_EXT_GRFX_MODE 0x57
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#define IGS_EXT_GRFX_MODE_EXT 0x01
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/* Overscan R/G/B registers */
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#define IGS_EXT_OVERSCAN_RED 0x58
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#define IGS_EXT_OVERSCAN_GREEN 0x59
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#define IGS_EXT_OVERSCAN_BLUE 0x5a
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/* Memory controller */
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#define IGS_EXT_MEM_CTL0 0x70
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#define IGS_EXT_MEM_CTL1 0x71
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#define IGS_EXT_MEM_CTL2 0x72
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/*
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* SEQ miscellaneous: number of SL between CCLK - controls visual depth.
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* These values are for MODE256 == 1, SRMODE = 1 in GRFX/5 mode register.
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*/
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#define IGS_EXT_SEQ_MISC 0x77
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#define IGS_EXT_SEQ_IBM_STD 0
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#define IGS_EXT_SEQ_8BPP 1 /* 256 indexed */
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#define IGS_EXT_SEQ_16BPP 2 /* HiColor 16bpp, 5-6-5 */
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#define IGS_EXT_SEQ_32BPP 3 /* TrueColor 32bpp */
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#define IGS_EXT_SEQ_24BPP 4 /* TrueColor 24bpp */
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#define IGS_EXT_SEQ_15BPP 6 /* HiColor 16bpp, 5-5-5 */
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/* Hardware cursor data location in linear memory */
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#define IGS_EXT_SPRITE_DATA_LO 0x7e
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#define IGS_EXT_SPRITE_DATA_HI 0x7f /* bits [3..0] */
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#define IGS_EXT_VCLK0 0xb0 /* mult */
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#define IGS_EXT_VCLK1 0xb1 /* div */
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#define IGS_EXT_MCLK0 0xb2 /* mult */
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#define IGS_EXT_MCLK1 0xb3 /* div */
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/* ----8<---- end of IGS_EXT registers ----8<---- */
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/*
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* CRTC can be at 0x3b4/0x3b5 (mono) or 0x3d4/0x3d5 (color)
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* controlled by bit 0 in misc output register (r=0x3cc/w=0x3c2).
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* We forcibly init it to color.
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*/
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#define IGS_CRTC_IDX IGS_REG_(0x3d4)
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#define IGS_CRTC_PORT IGS_REG_(0x3d5)
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/*
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* Reading this register resets flip-flop at 0x3c0 (attribute
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* controller) to address register.
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*/
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#define IGS_INPUT_STATUS1 IGS_REG_(0x3da)
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/*********************************************************************
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* IGS Graphic Coprocessor
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*/
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/*
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* Coprocessor registers location in I/O space.
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* Controlled by COPASELB bit in IGS_EXT_BIU_MISC_CTL.
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*/
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#define IGS_COP_BASE_A 0xafc00 /* COPASELB == 0 */
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#define IGS_COP_BASE_B 0xbfc00 /* COPASELB == 1 */
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#define IGS_COP_SIZE 0x00400
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/*
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* NB: Loaded width values should be 1 less than the actual width!
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*/
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/*
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* Coprocessor control.
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*/
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#define IGS_COP_CTL_REG 0x011
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#define IGS_COP_CTL_HBRDYZ 0x01
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#define IGS_COP_CTL_HFEMPTZ 0x02
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#define IGS_COP_CTL_CMDFF 0x04
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#define IGS_COP_CTL_SOP 0x08 /* rw */
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#define IGS_COP_CTL_OPS 0x10
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#define IGS_COP_CTL_TER 0x20 /* rw */
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#define IGS_COP_CTL_HBACKZ 0x40
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#define IGS_COP_CTL_BUSY 0x80
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/*
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* Source(s) and destination widths.
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* 16 bit registers. Only bits [11..0] are used.
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*/
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#define IGS_COP_SRC_MAP_WIDTH_REG 0x018
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#define IGS_COP_SRC2_MAP_WIDTH_REG 0x118
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#define IGS_COP_DST_MAP_WIDTH_REG 0x218
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/*
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* Bitmap depth.
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*/
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#define IGS_COP_MAP_FMT_REG 0x01c
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#define IGS_COP_MAP_8BPP 0x00
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#define IGS_COP_MAP_16BPP 0x01
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#define IGS_COP_MAP_24BPP 0x02
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#define IGS_COP_MAP_32BPP 0x03
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/*
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* Binary operations are defined below. S - source, D - destination,
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* N - not; a - and, o - or, x - xor.
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*
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* For ternary operations, foreground mix function is one of 256
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* ternary raster operations defined by Win32 API; background mix is
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* ignored.
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*/
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#define IGS_COP_FG_MIX_REG 0x048
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#define IGS_COP_BG_MIX_REG 0x049
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#define IGS_COP_MIX_0 0x0
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#define IGS_COP_MIX_SaD 0x1
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#define IGS_COP_MIX_SaND 0x2
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#define IGS_COP_MIX_S 0x3
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#define IGS_COP_MIX_NSaD 0x4
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#define IGS_COP_MIX_D 0x5
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#define IGS_COP_MIX_SxD 0x6
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#define IGS_COP_MIX_SoD 0x7
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#define IGS_COP_MIX_NSaND 0x8
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#define IGS_COP_MIX_SxND 0x9
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#define IGS_COP_MIX_ND 0xa
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#define IGS_COP_MIX_SoND 0xb
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#define IGS_COP_MIX_NS 0xc
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#define IGS_COP_MIX_NSoD 0xd
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#define IGS_COP_MIX_NSoND 0xe
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#define IGS_COP_MIX_1 0xf
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/*
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* Foreground/background colours (24 bit).
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* Selected by bits in IGS_COP_PIXEL_OP_3_REG.
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*/
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#define IGS_COP_FG_REG 0x058
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#define IGS_COP_BG_REG 0x05C
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/*
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* Horizontal/vertical dimentions of pixel blit function.
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* 16 bit registers. Only [11..0] are used.
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*/
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#define IGS_COP_WIDTH_REG 0x060
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#define IGS_COP_HEIGHT_REG 0x062
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/*
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* Only bits [21..0] are used.
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*/
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#define IGS_COP_SRC_BASE_REG 0x070 /* only for 24bpp Src Color Tiling */
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#define IGS_COP_SRC_START_REG 0x170
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#define IGS_COP_SRC2_START_REG 0x174
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#define IGS_COP_DST_START_REG 0x178
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/*
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* Destination phase angle for 24bpp.
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*/
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#define IGS_COP_DST_X_PHASE_REG 0x078
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#define IGS_COP_DST_X_PHASE_MASK 0x07
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/*
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* Pixel operation: Direction and draw mode.
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* When an octant bit is set, that axis is traversed backwards.
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*/
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#define IGS_COP_PIXEL_OP_0_REG 0x07c
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#define IGS_COP_OCTANT_Y_NEG 0x02 /* 0: top down, 1: bottom up */
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#define IGS_COP_OCTANT_X_NEG 0x04 /* 0: l2r, 1: r2l */
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#define IGS_COP_DRAW_ALL 0x00
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#define IGS_COP_DRAW_FIRST_NULL 0x10
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#define IGS_COP_DRAW_LAST_NULL 0x20
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/*
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* Pixel operation: Pattern operation.
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*/
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#define IGS_COP_PIXEL_OP_1_REG 0x07d
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#define IGS_COP_PPM_TEXT 0x10
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#define IGS_COP_PPM_TILE 0x20
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#define IGS_COP_PPM_LINE 0x30
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#define IGS_COP_PPM_TRANSPARENT 0x40 /* "or" with one of the above */
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#define IGS_COP_PPM_FIXED_FG 0x80
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#define IGS_COP_PPM_SRC_COLOR_TILE 0x90
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/*
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* Pixel operation: Host CPU access (host blit) to graphics engine.
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*/
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#define IGS_COP_PIXEL_OP_2_REG 0x07e
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#define IGS_COP_HBLTR 0x01 /* enable read from engine */
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#define IGS_COP_HBLTW 0x02 /* enable write to engine */
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/*
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* Pixel operation: Operation function of graphic engine.
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*/
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#define IGS_COP_PIXEL_OP_3_REG 0x07f
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#define IGS_COP_OP_STROKE 0x04 /* short stroke */
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#define IGS_COP_OP_LINE 0x05 /* bresenham line draw */
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#define IGS_COP_OP_PXBLT 0x08 /* pixel blit */
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#define IGS_COP_OP_PXBLT_INV 0x09 /* invert pixel blit */
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#define IGS_COP_OP_PXBLT_3 0x0a /* ternary pixel blit */
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/* select fg/bg source: 0 - fg/bg color reg, 1 - src1 map */
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#define IGS_COP_OP_FG_FROM_SRC 0x20
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#define IGS_COP_OP_BG_FROM_SRC 0x80
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#endif /* _DEV_IC_IGSFBREG_H_ */
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