174 lines
5.8 KiB
C
174 lines
5.8 KiB
C
/* $NetBSD: cxdtvreg.h,v 1.3 2015/07/11 10:32:46 kamil Exp $ */
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/*-
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* Copyright (c) 2007 Jared D. McNeill <jmcneill@invisible.ca>
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* Copyright (c) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_CXDTVREG_H
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#define _DEV_PCI_CXDTVREG_H
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/* misc. registers */
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#define CXDTV_PDMA_STHRSH 0x200000
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#define CXDTV_PDMA_STRGT_ADRS 0x200004
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#define CXDTV_PDMA_SINTL_ADRS 0x200008
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#define CXDTV_PDMA_SCNTRL 0x20000c
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#define CXDTV_PDMA_DTHRSH 0x200010
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#define CXDTV_PDMA_DTRGT_ADRS 0x200014
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#define CXDTV_PDMA_DINTL_ADRS 0x200018
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#define CXDTV_PDMA_DCNTRL 0x20001c
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#define CXDTV_LD_SUBSYS_ID_CFG 0x200030
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#define CXDTV_DEV_CNTRL2 0x200034
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#define CXDTV_PCI_INT_MASK 0x200040
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#define CXDTV_PCI_INT_STAT 0x200044
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#define CXDTV_PCI_INT_MSTAT 0x200048
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#define CXDTV_PLL_B 0x35c008
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#define CXDTV_GP0_IO 0x350010 /* GPIO */
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#define CXDTV_GP1_IO 0x350014
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#define CXDTV_GP2_IO 0x350018
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#define CXDTV_GP3_IO 0x35001c
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#define CXDTV_GPIO 0x350010 /* alt. GPIO mode */
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#define CXDTV_GPOE 0x350014
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#define CXDTV_GPIO_ISM 0x350028
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#define CXDTV_TM_CNT1_LDW 0x35c034
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#define CXDTV_TM_CNT1_UDW 0x35c038
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#define CXDTV_TM_LMT1_LDW 0x35c03c
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#define CXDTV_TM_LMT1_UDW 0x35c040
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#define CXDTV_PINMUX_IO 0x35c044
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#define CXDTV_AFE_CFG_IO 0x35c04c
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#define CXDTV_SRST_IO 0x35c05c
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#define CXDTV_I2C_C_DIRECT 0x360000 /* start; 0x367fff end */
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#define CXDTV_I2C_C_DATACONTROL 0x368000
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#define CXDTV_I2C_C_DATACONTROL_SDA 1
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#define CXDTV_I2C_C_DATACONTROL_SCL 2
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#define CXDTV_I2C_C_CTRL 0x36c004
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#define CXDTV_I2C_C_XFER_STATUS 0x36c044
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/* for CXDTV_PCI_INT_ registers */
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#define CXT_PI_VID_INT __BIT(0)
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#define CXT_PI_AUD_INT __BIT(1)
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#define CXT_PI_TS_INT __BIT(2)
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#define CXT_PI_VIP_INT __BIT(3)
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#define CXT_PI_HST_INT __BIT(4)
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#define CXDTV_DEV_CNTRL2_RUN_RISC __BIT(5)
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/* PINMUX_IO */
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#define MPEG_PAR_EN __BIT(7)
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/* MPEG TS registers */
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#define CXDTV_DMA28_PTR1 0x30009c
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#define CXDTV_DMA28_PTR2 0x3000dc
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#define CXDTV_DMA28_CNT1 0x30011c
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#define CXDTV_DMA28_CNT2 0x30015c
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#define CXDTV_TS_GP_CNT 0x33c020
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#define CXDTV_TS_GP_CNT_CNTRL 0x33c030
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#define CXDTV_TS_DMA_CNTRL 0x33c040
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#define CXDTV_TS_XFER_STATUS 0x33c044
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#define CXDTV_TS_LNGTH 0x33c048
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#define CXDTV_HW_SOP_CONTROL 0x33c04c
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#define CXDTV_TS_GEN_CONTROL 0x33c050
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#define CXDTV_TS_BD_PKT_STATUS 0x33c054
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#define CXDTV_TS_SOP_STATUS 0x33c058
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#define CXDTV_TS_FIFO_OVFL_STAT 0x33c05c
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#define CXDTV_TS_VLD_MISC 0x33c060
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#define CXDTV_TS_INT_MASK 0x200070
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#define CXDTV_TS_INT_STAT 0x200074
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#define CXDTV_TS_INT_MSTAT 0x200078
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#define CXDTV_TS_INT_SSTAT 0x20007c
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/* TS_DMA_CNTRL */
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#define CXDTV_TS_RISC_EN __BIT(4)
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#define CXDTV_TS_FIFO_EN __BIT(0)
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/* TS_INT_* */
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#define CXDTV_TS_RISCI2 __BIT(4)
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#define CXDTV_TS_RISCI1 __BIT(0)
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#define CXDTV_TS_RISCI (CXDTV_TS_RISCI2|CXDTV_TS_RISCI1)
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/* HW_SOP_CONTROL */
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/* TS_GEN_CONTROL */
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#define MPEG_IN_SYNC __BIT(0)
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#define IPB_MCLK_POL __BIT(1)
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#define IPB_PUNC_CLK __BIT(2)
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#define IPB_SMODE __BIT(3)
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#define IPB_BIT_RVRS __BIT(4)
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#define IPB_ERR_ACK __BIT(5)
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#define IPB_SW_RST __BIT(6)
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#define IPB_STAT_CLR __BIT(7)
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/* TS_SOP_STATUS */
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#define MPG_BAD_SOP_STAT __BITS(11,0)
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#define IPB_SOP_SYNC_CHK __BIT(12)
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#define IPB_SOP_BYTEWIDE __BIT(13)
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#define IPB_SOP_SEL __BITS(15, 14)
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#define IPB_TSSOP_POL __BIT(16)
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/* RISC instructions */
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#define CX_RISC_WRITECR 0xd0000000
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#define CX_RISC_WRITECM 0xc0000000
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#define CX_RISC_WRITERM 0xb0000000
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#define CX_RISC_READC 0xa0000000
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#define CX_RISC_READ 0x90000000
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#define CX_RISC_SYNC 0x80000000
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#define CX_RISC_JUMP 0x70000000
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#define CX_RISC_WRITEC 0x50000000
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#define CX_RISC_SKIP 0x20000000
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#define CX_RISC_WRITE 0x10000000
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#define CX_RISC_SOL 0x08000000
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#define CX_RISC_EOL 0x04000000
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#define CX_RISC_IRQ2 0x02000000
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#define CX_RISC_IRQ1 0x01000000
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#define CX_RISC_IMM 0x00000001
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#define CX_RISC_SRP 0x00000001
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#define CX_CNT_CTL_NOOP 0x0
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#define CX_CNT_CTL_INCR 0x1
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#define CX_CNT_CTL_ZERO 0x3
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#define CX_RISC_CNT_CTL __BITS(17,16)
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#define CX_RISC_CNT_CTL_NOOP __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_NOOP)
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#define CX_RISC_CNT_CTL_INCR __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_INCR)
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#define CX_RISC_CNT_CTL_ZERO __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_ZERO)
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/* Channel Management Data Structure */
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/* offsets */
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#define CX_CMDS_O_IRPC 0x00
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#define CX_CMDS_O_CDTB 0x04
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#define CX_CMDS_O_CDTS 0x08
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#define CX_CMDS_O_IQB 0x0c
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#define CX_CMDS_O_IQS 0x10
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/* bits */
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#define CX_CMDS_IQS_ISRP __BIT(31)
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/* PCI subsystems products */
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#define PCI_SUBSYSTEM_ATI_HDTV_WONDER 0xa101
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#define PCI_SUBSYSTEM_ATI_HDTV_WONDER_HP_Z556_MC 0xa103
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#endif /* !_DEV_PCI_CXDTVREG_H */
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