61 lines
2.3 KiB
C
61 lines
2.3 KiB
C
/* $NetBSD: dwc_mmc_var.h,v 1.5 2015/12/26 23:13:10 jmcneill Exp $ */
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/*-
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* Copyright (c) 2014 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _DWC_MMC_VAR_H
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#define _DWC_MMC_VAR_H
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struct dwc_mmc_softc {
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device_t sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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bus_dma_tag_t sc_dmat;
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void *sc_ih;
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unsigned int sc_clock_freq;
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unsigned int sc_clock_max;
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unsigned int sc_fifo_depth;
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uint32_t sc_flags;
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#define DWC_MMC_F_USE_HOLD_REG 0x0001 /* set USE_HOLD_REG with every cmd */
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#define DWC_MMC_F_PWREN_CLEAR 0x0002 /* clear POWER_ENABLE bit to enable */
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#define DWC_MMC_F_FORCE_CLK 0x0004 /* update clk div with every cmd */
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#define DWC_MMC_F_BROKEN_CD 0x0008 /* card detect doesn't work */
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int (*sc_set_clkdiv)(struct dwc_mmc_softc *, int);
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int (*sc_card_detect)(struct dwc_mmc_softc *);
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device_t sc_sdmmc_dev;
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kmutex_t sc_intr_lock;
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kcondvar_t sc_intr_cv;
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uint32_t sc_intr_rint;
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u_int sc_cur_freq;
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};
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void dwc_mmc_init(struct dwc_mmc_softc *);
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int dwc_mmc_intr(void *);
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#endif /* !_DWC_MMC_VAR_H */
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