419 lines
10 KiB
C
419 lines
10 KiB
C
/* $NetBSD: pci_machdep.c,v 1.6 2000/06/29 07:47:53 mrg Exp $ */
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/*
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* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
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* Copyright (c) 1994 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Machine-specific functions for PCI autoconfiguration.
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*
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* On PCs, there are two methods of generating PCI configuration cycles.
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* We try to detect the appropriate mechanism for this machine and set
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* up a few function pointers to access the correct method directly.
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/time.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <uvm/uvm_extern.h>
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#define _PREP_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <machine/pio.h>
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#include <machine/intr.h>
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#include <dev/isa/isavar.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#define PCI_MODE1_ENABLE 0x80000000UL
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#define PCI_MODE1_ADDRESS_REG (PREP_BUS_SPACE_IO + 0xcf8)
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#define PCI_MODE1_DATA_REG (PREP_BUS_SPACE_IO + 0xcfc)
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#define o2i(off) ((off)/sizeof(pcireg_t))
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/*
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* PCI doesn't have any special needs; just use the generic versions
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* of these functions.
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*/
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struct prep_bus_dma_tag pci_bus_dma_tag = {
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0, /* _bounce_thresh */
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_bus_dmamap_create,
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_bus_dmamap_destroy,
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_bus_dmamap_load,
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_bus_dmamap_load_mbuf,
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_bus_dmamap_load_uio,
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_bus_dmamap_load_raw,
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_bus_dmamap_unload,
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NULL, /* _dmamap_sync */
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_bus_dmamem_alloc,
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_bus_dmamem_free,
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_bus_dmamem_map,
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_bus_dmamem_unmap,
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_bus_dmamem_mmap,
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};
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void
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pci_attach_hook(parent, self, pba)
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struct device *parent, *self;
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struct pcibus_attach_args *pba;
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{
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pci_chipset_tag_t pc;
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int bus, device, maxndevs, function, nfunctions;
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int iq = 2; /* fixup ioaddr: 0x02000000~ */
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int mq = 1; /* fixup memaddr: 0x01000000~ */
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pc = pba->pba_pc;
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bus = pba->pba_bus;
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maxndevs = pci_bus_maxdevs(pba->pba_pc, pba->pba_bus);
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for (device = 0; device < maxndevs; device++) {
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pcitag_t tag;
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pcireg_t id, intr, bhlcr, csr, adr;
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int line;
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tag = pci_make_tag(pc, bus, device, 0);
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id = pci_conf_read(pc, tag, PCI_ID_REG);
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/* Invalid vendor ID value? */
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if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
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continue;
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/* XXX Not invalid, but we've done this ~forever. */
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if (PCI_VENDOR(id) == 0)
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continue;
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bhlcr = pci_conf_read(pc, tag, PCI_BHLC_REG);
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if (PCI_HDRTYPE_MULTIFN(bhlcr))
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nfunctions = 8;
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else
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nfunctions = 1;
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for (function = 0; function < nfunctions; function++) {
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pcireg_t regs[256/sizeof(pcireg_t)];
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pcireg_t mask;
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pcireg_t rval;
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int off;
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int memfound, iofound;
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tag = pci_make_tag(pc, bus, device, function);
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id = pci_conf_read(pc, tag, PCI_ID_REG);
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/* Invalid vendor ID value? */
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if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
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continue;
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/* XXX Not invalid, but we've done this ~forever. */
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if (PCI_VENDOR(id) == 0)
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continue;
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/* Enable io/mem */
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memfound = 0;
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iofound = 0;
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for (off = 0; off < 256; off += sizeof(pcireg_t))
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regs[o2i(off)] = pci_conf_read(pc, tag, off);
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/* is it a std device header? */
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if (PCI_HDRTYPE_TYPE(regs[o2i(PCI_BHLC_REG)]) != 0)
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continue;
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for (off = PCI_MAPREG_START;
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off < PCI_MAPREG_END; off += sizeof(pcireg_t)) {
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rval = regs[o2i(off)];
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if (rval != 0) {
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pci_conf_write(pc, tag, off, 0xffffffff);
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mask = pci_conf_read(pc, tag, off);
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pci_conf_write(pc, tag, off, rval);
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} else
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mask = 0;
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#ifdef DEBUG
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printf("\n");
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printf("dev %d func %d ", device, function);
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printf("off %02x addr %08x mask %08x",
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off, rval, mask);
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#endif
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if (rval == 0)
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continue;
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/* find IO or MEM space */
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if (PCI_MAPREG_TYPE(rval) == PCI_MAPREG_TYPE_MEM)
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memfound = 1;
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else
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iofound = 1;
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}
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if (memfound) {
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csr = pci_conf_read(pc, tag,
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PCI_COMMAND_STATUS_REG);
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csr |= PCI_COMMAND_MEM_ENABLE;
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pci_conf_write(pc, tag,
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PCI_COMMAND_STATUS_REG, csr);
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#ifdef DEBUG
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printf("\n");
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printf("dev %d func %d: mem", device, function);
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#endif
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}
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if (iofound) {
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csr = pci_conf_read(pc, tag,
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PCI_COMMAND_STATUS_REG);
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csr |= PCI_COMMAND_IO_ENABLE;
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pci_conf_write(pc, tag,
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PCI_COMMAND_STATUS_REG, csr);
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#ifdef DEBUG
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printf("\n");
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printf("dev %d func %d: io", device, function);
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#endif
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}
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/* Fixup insane address */
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for (off = PCI_MAPREG_START;
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off < PCI_MAPREG_END; off += sizeof(pcireg_t)) {
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int need_fixup;
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need_fixup = 0;
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adr = pci_conf_read(pc, tag, off);
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if (adr > 0x10000000 ||
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(adr < 0x1000 && adr != 0))
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need_fixup = 1;
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if (need_fixup) {
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#ifdef DEBUG
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printf("\n");
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printf("dev %d func %d %saddr %08x -> ",
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device, function,
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PCI_MAPREG_TYPE(adr) ==
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PCI_MAPREG_TYPE_MEM ? "mem":"io",
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adr);
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#endif
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adr &= 0x00ffffff;
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adr |= 0x01000000 *
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(PCI_MAPREG_TYPE(adr) ==
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PCI_MAPREG_TYPE_MEM ? mq++:iq++);
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#ifdef DEBUG
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printf("%08x", adr);
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#endif
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pci_conf_write(pc, tag, off, adr);
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}
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}
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/* Fixup intr */
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/* XXX: ibm_machdep : ppc830 depend */
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switch (device) {
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case 12:
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case 18:
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case 22:
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line = 15;
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break;
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default:
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line = 0;
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break;
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}
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if (line) {
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intr = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
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pci_conf_write(pc, tag, PCI_INTERRUPT_REG,
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(intr & ~0xff) | line);
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}
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}
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}
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}
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int
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pci_bus_maxdevs(pc, busno)
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pci_chipset_tag_t pc;
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int busno;
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{
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/*
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* Bus number is irrelevant. Configuration Mechanism 1 is in
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* use, can have devices 0-32 (i.e. the `normal' range).
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*/
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return (32);
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}
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pcitag_t
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pci_make_tag(pc, bus, device, function)
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pci_chipset_tag_t pc;
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int bus, device, function;
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{
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pcitag_t tag;
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if (bus >= 256 || device >= 32 || function >= 8)
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panic("pci_make_tag: bad request");
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tag = PCI_MODE1_ENABLE |
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(bus << 16) | (device << 11) | (function << 8);
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return tag;
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}
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void
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pci_decompose_tag(pc, tag, bp, dp, fp)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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int *bp, *dp, *fp;
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{
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if (bp != NULL)
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*bp = (tag >> 16) & 0xff;
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if (dp != NULL)
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*dp = (tag >> 11) & 0x1f;
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if (fp != NULL)
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*fp = (tag >> 8) & 0x7;
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return;
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}
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pcireg_t
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pci_conf_read(pc, tag, reg)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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int reg;
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{
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pcireg_t data;
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out32rb(PCI_MODE1_ADDRESS_REG, tag | reg);
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data = in32rb(PCI_MODE1_DATA_REG);
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out32rb(PCI_MODE1_ADDRESS_REG, 0);
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return data;
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}
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void
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pci_conf_write(pc, tag, reg, data)
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pci_chipset_tag_t pc;
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pcitag_t tag;
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int reg;
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pcireg_t data;
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{
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out32rb(PCI_MODE1_ADDRESS_REG, tag | reg);
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out32rb(PCI_MODE1_DATA_REG, data);
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out32rb(PCI_MODE1_ADDRESS_REG, 0);
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}
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int
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pci_intr_map(pc, intrtag, pin, line, ihp)
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pci_chipset_tag_t pc;
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pcitag_t intrtag;
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int pin, line;
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pci_intr_handle_t *ihp;
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{
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if (pin == 0) {
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/* No IRQ used. */
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goto bad;
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}
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if (pin > 4) {
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printf("pci_intr_map: bad interrupt pin %d\n", pin);
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goto bad;
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}
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/*
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* Section 6.2.4, `Miscellaneous Functions', says that 255 means
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* `unknown' or `no connection' on a PC. We assume that a device with
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* `no connection' either doesn't have an interrupt (in which case the
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* pin number should be 0, and would have been noticed above), or
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* wasn't configured by the BIOS (in which case we punt, since there's
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* no real way we can know how the interrupt lines are mapped in the
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* hardware).
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*
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* XXX
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* Since IRQ 0 is only used by the clock, and we can't actually be sure
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* that the BIOS did its job, we also recognize that as meaning that
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* the BIOS has not configured the device.
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*/
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if (line == 0 || line == 255) {
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printf("pci_intr_map: no mapping for pin %c\n", '@' + pin);
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goto bad;
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} else {
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if (line >= ICU_LEN) {
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printf("pci_intr_map: bad interrupt line %d\n", line);
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goto bad;
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}
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if (line == IRQ_SLAVE) {
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printf("pci_intr_map: changed line 2 to line 9\n");
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line = 9;
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}
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}
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*ihp = line;
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return 0;
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bad:
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*ihp = -1;
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return 1;
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}
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const char *
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pci_intr_string(pc, ih)
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pci_chipset_tag_t pc;
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pci_intr_handle_t ih;
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{
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static char irqstr[8]; /* 4 + 2 + NULL + sanity */
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if (ih == 0 || ih >= ICU_LEN || ih == IRQ_SLAVE)
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panic("pci_intr_string: bogus handle 0x%x\n", ih);
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sprintf(irqstr, "irq %d", ih);
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return (irqstr);
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}
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const struct evcnt *
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pci_intr_evcnt(pc, ih)
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pci_chipset_tag_t pc;
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pci_intr_handle_t ih;
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{
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/* XXX for now, no evcnt parent reported */
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return NULL;
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}
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void *
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pci_intr_establish(pc, ih, level, func, arg)
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pci_chipset_tag_t pc;
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pci_intr_handle_t ih;
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int level, (*func) __P((void *));
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void *arg;
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{
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if (ih == 0 || ih >= ICU_LEN || ih == IRQ_SLAVE)
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panic("pci_intr_establish: bogus handle 0x%x\n", ih);
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return isa_intr_establish(NULL, ih, IST_LEVEL, level, func, arg);
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}
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void
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pci_intr_disestablish(pc, cookie)
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pci_chipset_tag_t pc;
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void *cookie;
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{
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return isa_intr_disestablish(NULL, cookie);
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}
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