47ef6a5146
bus_space_handle_t now holds an address and two ASIs, one for normal accesses and one for streaming accesses. This allows to map individual handles different ways, so some can use MMU bypass accesses and others use virtual addresses. bus_space_map() will now create handles that use bypass accesses unles BUS_SPACE_MAP_LINEAR is passed in. So only pass in BUS_SPACE_MAP_LINEAR if you absolutely *need* to use bus_space_vaddr(). This removes at least one extra level of indirection and should reduce TLB misses. 32-bit kernels have problems accessing 64-bit addresses, so they always use virtual addresses.
164 lines
6.8 KiB
C
164 lines
6.8 KiB
C
/* $NetBSD: iommureg.h,v 1.8 2002/03/20 18:54:47 eeh Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)sbusreg.h 8.1 (Berkeley) 6/11/93
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*/
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#ifndef _SPARC64_DEV_IOMMUREG_H_
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#define _SPARC64_DEV_IOMMUREG_H_
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/*
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* UltraSPARC IOMMU registers, common to both the sbus and PCI
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* controllers.
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*/
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/* iommmu registers */
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struct iommureg {
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u_int64_t iommu_cr; /* IOMMU control register */
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u_int64_t iommu_tsb; /* IOMMU TSB base register */
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u_int64_t iommu_flush; /* IOMMU flush register */
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};
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/* streaming buffer registers */
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struct iommu_strbuf {
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u_int64_t strbuf_ctl; /* streaming buffer control reg */
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u_int64_t strbuf_pgflush; /* streaming buffer page flush */
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u_int64_t strbuf_flushsync;/* streaming buffer flush sync */
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};
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#define IOMMUREG(x) (offsetof(struct iommureg, x))
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#define STRBUFREG(x) (offsetof(struct iommu_strbuf, x))
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/* streaming buffer control register */
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#define STRBUF_EN 0x000000000000000001LL
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#define STRBUF_D 0x000000000000000002LL
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/* control register bits */
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#define IOMMUCR_TSB1K 0x000000000000000000LL /* Nummber of entries in IOTSB */
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#define IOMMUCR_TSB2K 0x000000000000010000LL
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#define IOMMUCR_TSB4K 0x000000000000020000LL
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#define IOMMUCR_TSB8K 0x000000000000030000LL
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#define IOMMUCR_TSB16K 0x000000000000040000LL
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#define IOMMUCR_TSB32K 0x000000000000050000LL
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#define IOMMUCR_TSB64K 0x000000000000060000LL
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#define IOMMUCR_TSB128K 0x000000000000070000LL
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#define IOMMUCR_TSBMASK 0xfffffffffffff8ffffLL /* Mask for above */
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#define IOMMUCR_8KPG 0x000000000000000000LL /* 8K iommu page size */
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#define IOMMUCR_64KPG 0x000000000000000004LL /* 64K iommu page size */
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#define IOMMUCR_DE 0x000000000000000002LL /* Diag enable */
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#define IOMMUCR_EN 0x000000000000000001LL /* Enable IOMMU */
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/*
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* IOMMU stuff
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*/
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#define IOTTE_V 0x8000000000000000LL /* Entry valid */
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#define IOTTE_64K 0x2000000000000000LL /* 8K or 64K page? */
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#define IOTTE_8K 0x0000000000000000LL
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#define IOTTE_STREAM 0x1000000000000000LL /* Is page streamable? */
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#define IOTTE_LOCAL 0x0800000000000000LL /* Accesses to same bus segment? */
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#define IOTTE_PAMASK 0x000001ffffffe000LL /* Let's assume this is correct */
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#define IOTTE_C 0x0000000000000010LL /* Accesses to cacheable space */
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#define IOTTE_W 0x0000000000000002LL /* Writeable */
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/*
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* On sun4u each bus controller has a separate IOMMU. The IOMMU has
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* a TSB which must be page aligned and physically contiguous. Mappings
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* can be of 8K IOMMU pages or 64K IOMMU pages. We use 8K for compatibility
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* with the CPU's MMU.
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*
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* On sysio, psycho, and psycho+, IOMMU TSBs using 8K pages can map the
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* following size segments:
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*
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* VA size VA base TSB size tsbsize
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* -------- -------- --------- -------
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* 8MB ff800000 8K 0
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* 16MB ff000000 16K 1
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* 32MB fe000000 32K 2
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* 64MB fc000000 64K 3
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* 128MB f8000000 128K 4
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* 256MB f0000000 256K 5
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* 512MB e0000000 512K 6
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* 1GB c0000000 1MB 7
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*
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* Unfortunately, sabres on UltraSPARC IIi and IIe processors does not use
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* this scheme to determine the IOVA base address. Instead, bits 31-29 are
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* used to check against the Target Address Space register in the IIi and
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* the the IOMMU is used if they hit. God knows what goes on in the IIe.
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*
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*/
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#define IOTSB_VEND (u_int)(0xffffffffffffffffLL<<PGSHIFT)
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#define IOTSB_VSTART(sz) (u_int)(IOTSB_VEND << ((sz)+10))
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#define IOTSB_VSIZE(sz) (u_int)(1 << ((sz)+10+PGSHIFT))
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#define MAKEIOTTE(pa,w,c,s) (((pa)&IOTTE_PAMASK)|((w)?IOTTE_W:0)|((c)?IOTTE_C:0)|((s)?IOTTE_STREAM:0)|(IOTTE_V|IOTTE_8K))
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#define IOTSBSLOT(va,sz) ((u_int)(((vaddr_t)(va))-(is->is_dvmabase))>>PGSHIFT)
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/*
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* interrupt map stuff. this belongs elsewhere.
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*/
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#define INTMAP_V 0x080000000LL /* Interrupt valid (enabled) */
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#define INTMAP_TID 0x07c000000LL /* UPA target ID mask */
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#define INTMAP_IGN 0x0000007c0LL /* Interrupt group no (sbus only). */
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#define INTMAP_INO 0x00000003fLL /* Interrupt number */
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#define INTMAP_INR (INTMAP_IGN|INTMAP_INO)
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#define INTMAP_SBUSSLOT 0x000000018LL /* SBUS slot # */
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#define INTMAP_PCIBUS 0x000000010LL /* PCI bus number (A or B) */
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#define INTMAP_PCISLOT 0x00000000cLL /* PCI slot # */
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#define INTMAP_PCIINT 0x000000003LL /* PCI interrupt #A,#B,#C,#D */
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#define INTMAP_OBIO 0x000000020LL /* Onboard device */
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#define INTMAP_LSHIFT 11 /* Encode level in vector */
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#define INTLEVENCODE(x) (((x)&0x0f)<<INTMAP_LSHIFT)
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#define INTLEV(x) (((x)>>INTMAP_LSHIFT)&0x0f)
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#define INTVEC(x) ((x)&INTMAP_INR)
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#define INTSLOT(x) (((x)>>3)&0x7)
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#define INTPRI(x) ((x)&0x7)
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#define INTINO(x) ((x)&INTMAP_INO)
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#define INTPCI_MAXOBINO 0x16 /* maximum OBIO INO value for PCI */
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#define INTPCIOBINOX(x) ((x)&0x1f) /* OBIO ino index (for PCI machines) */
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#define INTPCIINOX(x) (((x)&0x1c)>>2) /* PCI ino index */
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#endif /* _SPARC64_DEV_IOMMUREG_H_ */
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