71 lines
2.7 KiB
C
71 lines
2.7 KiB
C
/* $NetBSD: fpu_status.h,v 1.2 1997/04/01 16:35:12 matthias Exp $ */
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/*
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* IEEE floating point support for NS32081 and NS32381 fpus.
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* Copyright (c) 1995 Ian Dall
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* IAN DALL ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" CONDITION.
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* IAN DALL DISCLAIMS ANY LIABILITY OF ANY KIND FOR ANY DAMAGES
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* WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*/
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/*
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* File: fpu_status.h
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* Author: Ian Dall
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* Date: November 1995
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*
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* FPU status register definitions
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*
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* HISTORY
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* 14-Dec-95 Ian Dall (Ian.Dall@dsto.defence.gov.au)
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* First release.
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*
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*/
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#ifndef _FPU_STATUS_H_
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#define _FPU_STATUS_H_
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/*
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* Control register
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*/
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#define FPC_RMB 0x00010000 /* register modify bit */
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#define FPC_SWF 0x0000fe00 /* reserved for software */
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#define FPC_RM 0x00000180 /* rounding mode */
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#define FPC_RM_NEAREST 0x00000000 /* round to nearest */
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#define FPC_RM_TOZERO 0x00000080 /* round towards zero */
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#define FPC_RM_TOPOS 0x00000100 /* round towards +infinity */
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#define FPC_RM_TONEG 0x00000180 /* round towards -infinity */
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#define FPC_IF 0x00000040 /* inexact result flag */
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#define FPC_IEN 0x00000020 /* inexact result trap enable */
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#define FPC_UF 0x00000010 /* underflow flag (else 0) */
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#define FPC_UEN 0x00000008 /* underflow trap enable */
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#define FPC_TT 0x00000007 /* trap type mask */
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#define FPC_TT_NONE 0x00000000 /* no exceptional condition */
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#define FPC_TT_UNDFL 0x00000001 /* underflow */
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#define FPC_TT_OVFL 0x00000002 /* overflow */
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#define FPC_TT_DIV0 0x00000003 /* divide by zero */
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#define FPC_TT_ILL 0x00000004 /* illegal instruction */
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#define FPC_TT_INVOP 0x00000005 /* invalid operation */
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#define FPC_TT_INEXACT 0x00000006 /* inexact result */
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#define FPC_TT_UNKNOWN 0x00000007 /* Not a real trap type */
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/* Bits in the SWF field used for software emulation */
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#define FPC_OVE 0x200 /* Overflow enable */
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#define FPC_OVF 0x400 /* Overflow flag */
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#define FPC_IVE 0x800 /* Invalid enable */
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#define FPC_IVF 0x1000 /* Invalid flag */
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#define FPC_DZE 0x2000 /* Divide by zero enable */
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#define FPC_DZF 0x4000 /* Divide by zero flag */
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#define FPC_UNDE 0x8000 /* Soft Underflow enable, requires FPC_UEN */
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#define GET_SET_FSR(val) ({int _tmp; asm volatile("sfsr %0; lfsr %1" : "&=g" (_tmp): "g" (val)); _tmp;})
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#define GET_FSR() ({int _tmp; asm volatile("sfsr %0" : "=g" (_tmp)); _tmp;})
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#define SET_FSR(val) ({asm volatile("lfsr %0" :: "g" (val));})
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#endif /* _FPU_STATUS_H_ */
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