554 lines
15 KiB
C
554 lines
15 KiB
C
/* $NetBSD: asc.c,v 1.12 2002/10/02 05:38:10 thorpej Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Wayne Knowles
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <sys/malloc.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/scsipi/scsi_message.h>
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#include <machine/cpu.h>
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#include <machine/autoconf.h>
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#include <machine/mainboard.h>
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#include <machine/bus.h>
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#include <mipsco/obio/rambo.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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struct asc_softc {
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struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */
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struct evcnt sc_intrcnt; /* Interrupt counter */
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh; /* NCR 53c94 registers */
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bus_space_handle_t dm_bsh; /* RAMBO registers */
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bus_dma_tag_t sc_dmat;
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bus_dmamap_t sc_dmamap;
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caddr_t *sc_dmaaddr;
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size_t *sc_dmalen;
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size_t sc_dmasize;
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int sc_flags;
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#define DMA_IDLE 0x0
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#define DMA_PULLUP 0x1
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#define DMA_ACTIVE 0x2
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#define DMA_MAPLOADED 0x4
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u_int32_t dm_mode;
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int dm_curseg;
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};
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static int ascmatch (struct device *, struct cfdata *, void *);
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static void ascattach (struct device *, struct device *, void *);
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CFATTACH_DECL(asc, sizeof(struct asc_softc),
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ascmatch, ascattach, NULL, NULL);
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/*
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* Functions and the switch for the MI code.
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*/
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static u_char asc_read_reg (struct ncr53c9x_softc *, int);
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static void asc_write_reg (struct ncr53c9x_softc *, int, u_char);
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static int asc_dma_isintr (struct ncr53c9x_softc *);
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static void asc_dma_reset (struct ncr53c9x_softc *);
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static int asc_dma_intr (struct ncr53c9x_softc *);
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static int asc_dma_setup (struct ncr53c9x_softc *, caddr_t *,
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size_t *, int, size_t *);
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static void asc_dma_go (struct ncr53c9x_softc *);
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static void asc_dma_stop (struct ncr53c9x_softc *);
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static int asc_dma_isactive (struct ncr53c9x_softc *);
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static struct ncr53c9x_glue asc_glue = {
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asc_read_reg,
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asc_write_reg,
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asc_dma_isintr,
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asc_dma_reset,
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asc_dma_intr,
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asc_dma_setup,
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asc_dma_go,
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asc_dma_stop,
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asc_dma_isactive,
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NULL, /* gl_clear_latched_intr */
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};
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static int asc_intr (void *);
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#define MAX_SCSI_XFER (64*1024)
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#define MAX_DMA_SZ MAX_SCSI_XFER
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#define DMA_SEGS (MAX_DMA_SZ/NBPG)
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static int
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ascmatch(struct device *parent, struct cfdata *cf, void *aux)
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{
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return 1;
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}
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static void
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ascattach(struct device *parent, struct device *self, void *aux)
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{
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struct confargs *ca = aux;
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struct asc_softc *esc = (void *)self;
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struct ncr53c9x_softc *sc = &esc->sc_ncr53c9x;
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/*
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* Set up glue for MI code early; we use some of it here.
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*/
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sc->sc_glue = &asc_glue;
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esc->sc_bst = ca->ca_bustag;
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esc->sc_dmat = ca->ca_dmatag;
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if (bus_space_map(ca->ca_bustag, ca->ca_addr,
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16*4, /* sizeof (ncr53c9xreg) */
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BUS_SPACE_MAP_LINEAR,
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&esc->sc_bsh) != 0) {
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printf(": cannot map registers\n");
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return;
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}
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if (bus_space_map(ca->ca_bustag, RAMBO_BASE, sizeof(struct rambo_ch),
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BUS_SPACE_MAP_LINEAR,
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&esc->dm_bsh) != 0) {
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printf(": cannot map dma registers\n");
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return;
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}
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if (bus_dmamap_create(esc->sc_dmat, MAX_DMA_SZ,
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DMA_SEGS, MAX_DMA_SZ, RB_BOUNDRY,
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BUS_DMA_WAITOK,
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&esc->sc_dmamap) != 0) {
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printf(": failed to create dmamap\n");
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return;
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}
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evcnt_attach_dynamic(&esc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
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self->dv_xname, "intr");
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esc->sc_flags = DMA_IDLE;
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asc_dma_reset(sc);
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/* Other settings */
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sc->sc_id = 7;
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sc->sc_freq = 24; /* 24 MHz clock */
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/*
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* Setup for genuine NCR 53C94 SCSI Controller
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*/
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sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB;
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sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE;
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sc->sc_cfg3 = NCRCFG3_CDB | NCRCFG3_QTE | NCRCFG3_FSCSI;
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sc->sc_rev = NCR_VARIANT_NCR53C94;
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sc->sc_minsync = (1000 / sc->sc_freq) * 5 / 4;
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sc->sc_maxxfer = MAX_SCSI_XFER;
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#ifdef OLDNCR
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if (!NCR_READ_REG(sc, NCR_CFG3)) {
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printf(" [old revision]");
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sc->sc_cfg2 = 0;
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sc->sc_cfg3 = 0;
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sc->sc_minsync = 0;
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}
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#endif
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sc->sc_adapter.adapt_minphys = minphys;
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sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request;
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ncr53c9x_attach(sc);
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bus_intr_establish(esc->sc_bst, SYS_INTR_SCSI, 0, 0, asc_intr, esc);
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}
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/*
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* Glue functions.
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*/
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static u_char
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asc_read_reg(struct ncr53c9x_softc *sc, int reg)
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{
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struct asc_softc *esc = (struct asc_softc *)sc;
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return bus_space_read_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3);
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}
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static void
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asc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val)
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{
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struct asc_softc *esc = (struct asc_softc *)sc;
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bus_space_write_1(esc->sc_bst, esc->sc_bsh, reg * 4 + 3, val);
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}
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static void
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dma_status(struct ncr53c9x_softc *sc)
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{
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struct asc_softc *esc = (struct asc_softc *)sc;
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int count;
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int stat;
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void *addr;
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u_int32_t tc;
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tc = (asc_read_reg(sc, NCR_TCM)<<8) + asc_read_reg(sc, NCR_TCL);
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count = bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT);
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stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE);
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addr = (void *)
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bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_CADDR);
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printf("rambo status: cnt=%x addr=%p stat=%08x tc=%04x "
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"ncr_stat=0x%02x ncr_fifo=0x%02x\n",
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count, addr, stat, tc,
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asc_read_reg(sc, NCR_STAT),
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asc_read_reg(sc, NCR_FFLAG));
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}
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static __inline void
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check_fifo(struct asc_softc *esc)
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{
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register int i=100;
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while (i && !(bus_space_read_4(esc->sc_bst, esc->dm_bsh,
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RAMBO_MODE) & RB_FIFO_EMPTY)) {
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DELAY(1); i--;
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}
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if (!i) {
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dma_status((void *)esc);
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panic("fifo didn't flush");
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}
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}
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static int
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asc_dma_isintr(struct ncr53c9x_softc *sc)
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{
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return NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT;
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}
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static void
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asc_dma_reset(struct ncr53c9x_softc *sc)
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{
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struct asc_softc *esc = (struct asc_softc *)sc;
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bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0);
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bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE,
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RB_CLRFIFO|RB_CLRERROR);
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DELAY(10);
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bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0);
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if (esc->sc_flags & DMA_MAPLOADED)
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bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap);
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esc->sc_flags = DMA_IDLE;
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}
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/*
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* Setup a DMA transfer
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*/
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static int
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asc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len,
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int datain, size_t *dmasize)
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{
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struct asc_softc *esc = (struct asc_softc *)sc;
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paddr_t paddr;
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size_t count, blocks;
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int prime, err;
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#ifdef DIAGNOSTIC
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if (esc->sc_flags & DMA_ACTIVE) {
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dma_status(sc);
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panic("DMA active");
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}
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#endif
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esc->sc_dmaaddr = addr;
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esc->sc_dmalen = len;
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esc->sc_dmasize = *dmasize;
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esc->sc_flags = datain ? DMA_PULLUP : 0;
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NCR_DMA(("asc_dma_setup va=%p len=%d datain=%d count=%d\n",
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*addr, *len, datain, esc->sc_dmasize));
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if (esc->sc_dmasize == 0)
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return 0;
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/* have dmamap for the transfering addresses */
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if ((err=bus_dmamap_load(esc->sc_dmat, esc->sc_dmamap,
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*esc->sc_dmaaddr, esc->sc_dmasize,
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NULL /* kernel address */,
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BUS_DMA_NOWAIT)) != 0)
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panic("%s: bus_dmamap_load err=%d", sc->sc_dev.dv_xname, err);
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esc->sc_flags |= DMA_MAPLOADED;
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paddr = esc->sc_dmamap->dm_segs[0].ds_addr;
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count = esc->sc_dmamap->dm_segs[0].ds_len;
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prime = (u_int32_t)paddr & 0x3f;
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blocks = (prime + count + 63) >> 6;
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esc->dm_mode = (datain ? RB_DMA_WR : RB_DMA_RD);
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/* Set transfer direction and disable DMA */
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bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode);
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/* Load DMA transfer address */
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bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR,
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paddr & ~0x3f);
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/* Load number of blocks to DMA (1 block = 64 bytes) */
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bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks);
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/* If non block-aligned transfer prime FIFO manually */
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if (prime) {
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/* Enable DMA to prime the FIFO buffer */
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bus_space_write_4(esc->sc_bst, esc->dm_bsh,
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RAMBO_MODE, esc->dm_mode | RB_DMA_ENABLE);
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if (esc->sc_flags & DMA_PULLUP) {
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/* Read from NCR 53c94 controller*/
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u_int16_t *p;
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p = (u_int16_t *)((u_int32_t)*esc->sc_dmaaddr & ~0x3f);
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bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh,
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RAMBO_FIFO, p, prime>>1);
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} else
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/* Write to NCR 53C94 controller */
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while (prime > 0) {
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(void)bus_space_read_2(esc->sc_bst,
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esc->dm_bsh,
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RAMBO_FIFO);
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prime -= 2;
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}
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/* Leave DMA disabled while we setup NCR controller */
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bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE,
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esc->dm_mode);
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}
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bus_dmamap_sync(esc->sc_dmat, esc->sc_dmamap, 0, esc->sc_dmasize,
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datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
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esc->dm_curseg = 0;
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esc->dm_mode |= RB_DMA_ENABLE;
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if (esc->sc_dmamap->dm_nsegs > 1)
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esc->dm_mode |= RB_INT_ENABLE; /* Requires DMA chaining */
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return 0;
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}
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static void
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asc_dma_go(struct ncr53c9x_softc *sc)
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{
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struct asc_softc *esc = (struct asc_softc *)sc;
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/* Start DMA */
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bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, esc->dm_mode);
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esc->sc_flags |= DMA_ACTIVE;
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}
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static int
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asc_dma_intr(struct ncr53c9x_softc *sc)
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{
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struct asc_softc *esc = (struct asc_softc *)sc;
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size_t resid, len;
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int trans;
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u_int32_t status;
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u_int tcl, tcm;
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#ifdef DIAGNOSTIC
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if (!(esc->sc_flags & DMA_ACTIVE)) {
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dma_status(sc);
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panic("DMA not active");
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}
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#endif
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resid = 0;
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if (!(esc->sc_flags & DMA_PULLUP) &&
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(resid = (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
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NCR_DMA(("asc_intr: empty FIFO of %d ", resid));
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DELAY(10);
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}
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resid += (tcl = NCR_READ_REG(sc, NCR_TCL)) +
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((tcm = NCR_READ_REG(sc, NCR_TCM)) << 8);
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if (esc->sc_dmasize == 0) { /* Transfer pad operation */
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NCR_DMA(("asc_intr: discard %d bytes\n", resid));
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return 0;
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}
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trans = esc->sc_dmasize - resid;
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if (trans < 0) { /* transferred < 0 ? */
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printf("asc_intr: xfer (%d) > req (%d)\n",
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trans, esc->sc_dmasize);
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trans = esc->sc_dmasize;
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}
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NCR_DMA(("asc_intr: tcl=%d, tcm=%d; trans=%d, resid=%d\n",
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tcl, tcm, trans, resid));
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status = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE);
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if (!(status & RB_FIFO_EMPTY)) { /* Data left in RAMBO FIFO */
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if (esc->sc_flags & DMA_PULLUP) { /* SCSI Read */
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paddr_t ptr;
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u_int16_t *p;
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resid = status & 0x1f;
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/* take the address of block to fixed up */
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ptr = bus_space_read_4(esc->sc_bst, esc->dm_bsh,
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RAMBO_CADDR);
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/* find the starting address of fractional data */
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p = (u_int16_t *)MIPS_PHYS_TO_KSEG0(ptr+(resid<<1));
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/* duplicate trailing data to FIFO for force flush */
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len = RB_BLK_CNT - resid;
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bus_space_write_multi_2(esc->sc_bst, esc->dm_bsh,
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RAMBO_FIFO, p, len);
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check_fifo(esc);
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} else { /* SCSI Write */
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bus_space_write_4(esc->sc_bst, esc->dm_bsh,
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RAMBO_MODE, 0);
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bus_space_write_4(esc->sc_bst, esc->dm_bsh,
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RAMBO_MODE, RB_CLRFIFO);
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}
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}
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bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, 0);
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bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0);
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bus_dmamap_sync(esc->sc_dmat, esc->sc_dmamap,
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0, esc->sc_dmasize,
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(esc->sc_flags & DMA_PULLUP)
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? BUS_DMASYNC_POSTREAD
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: BUS_DMASYNC_POSTWRITE);
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bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap);
|
|
|
|
*esc->sc_dmaaddr += trans;
|
|
*esc->sc_dmalen -= trans;
|
|
|
|
esc->sc_flags = DMA_IDLE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
static void
|
|
asc_dma_stop(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct asc_softc *esc = (struct asc_softc *)sc;
|
|
|
|
bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE, 0);
|
|
if (esc->sc_flags & DMA_MAPLOADED)
|
|
bus_dmamap_unload(esc->sc_dmat, esc->sc_dmamap);
|
|
esc->sc_flags = DMA_IDLE;
|
|
}
|
|
|
|
static int
|
|
asc_dma_isactive(struct ncr53c9x_softc *sc)
|
|
{
|
|
struct asc_softc *esc = (struct asc_softc *)sc;
|
|
return (esc->sc_flags & DMA_ACTIVE)? 1 : 0;
|
|
}
|
|
|
|
static void
|
|
rambo_dma_chain(struct asc_softc *esc)
|
|
{
|
|
int seg;
|
|
size_t count, blocks;
|
|
paddr_t paddr;
|
|
|
|
seg = ++esc->dm_curseg;
|
|
|
|
#ifdef DIAGNOSTIC
|
|
if (!(esc->sc_flags & DMA_ACTIVE) || seg > esc->sc_dmamap->dm_nsegs)
|
|
panic("Unexpected DMA chaining intr");
|
|
|
|
/* Interrupt can only occur at terminal count, but double check */
|
|
if (bus_space_read_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT)) {
|
|
dma_status((void *)esc);
|
|
panic("rambo blkcnt != 0");
|
|
}
|
|
#endif
|
|
|
|
paddr = esc->sc_dmamap->dm_segs[seg].ds_addr;
|
|
count = esc->sc_dmamap->dm_segs[seg].ds_len;
|
|
blocks = (count + 63) >> 6;
|
|
|
|
/* Disable DMA interrupt if last segment */
|
|
if (seg+1 > esc->sc_dmamap->dm_nsegs) {
|
|
bus_space_write_4(esc->sc_bst, esc->dm_bsh,
|
|
RAMBO_MODE, esc->dm_mode & ~RB_INT_ENABLE);
|
|
}
|
|
|
|
/* Load transfer address for next DMA chain */
|
|
bus_space_write_4(esc->sc_bst, esc->dm_bsh, RAMBO_LADDR, paddr);
|
|
|
|
/* DMA restarts when we enter a new block count */
|
|
bus_space_write_2(esc->sc_bst, esc->dm_bsh, RAMBO_BLKCNT, blocks);
|
|
}
|
|
|
|
static int
|
|
asc_intr(void *arg)
|
|
{
|
|
register u_int32_t dma_stat;
|
|
struct asc_softc *esc = arg;
|
|
struct ncr53c9x_softc *sc = arg;
|
|
|
|
esc->sc_intrcnt.ev_count++;
|
|
|
|
/* Check for RAMBO DMA Interrupt */
|
|
dma_stat = bus_space_read_4(esc->sc_bst, esc->dm_bsh, RAMBO_MODE);
|
|
if (dma_stat & RB_INTR_PEND) {
|
|
rambo_dma_chain(esc);
|
|
}
|
|
/* Check for NCR 53c94 interrupt */
|
|
if (NCR_READ_REG(sc, NCR_STAT) & NCRSTAT_INT) {
|
|
ncr53c9x_intr(sc);
|
|
}
|
|
return 0;
|
|
}
|