41f47f03e7
I/O processors: * The i80200 and the i80321 have the same CPU ID, so split the CPU_XSCALE option into CPU_XSCALE_80200 and CPU_XSCALE_80321 options, and don't let them both be defined at the same time. XXX May want to revisit this in the future. * Split some registers common between the i80200 and i80321 into <arm/xscale/xscalereg.h>. * Rename a few existing functions.
125 lines
3.3 KiB
C
125 lines
3.3 KiB
C
/* $NetBSD: i80200_icu.c,v 1.4 2002/03/26 19:29:46 thorpej Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Intel i80200 Interrupt Controller Unit support.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <arm/cpufunc.h>
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#include <arm/xscale/i80200reg.h>
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#include <arm/xscale/i80200var.h>
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/* Software shadow copy of INTCTL. */
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static __volatile uint32_t intctl;
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/* Pointer to board-specific external IRQ dispatcher. */
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void (*i80200_extirq_dispatch)(struct clockframe *);
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static void
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i80200_default_extirq_dispatch(struct clockframe *framep)
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{
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panic("external IRQ with no dispatch routine");
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}
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/*
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* i80200_icu_init:
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*
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* Initialize the i80200 ICU.
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*/
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void
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i80200_icu_init(void)
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{
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/* Disable all interrupt sources. */
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intctl = 0;
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__asm __volatile("mcr p13, 0, %0, c0, c0"
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:
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: "r" (intctl));
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/* Steer PMU and BMU to IRQ. */
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__asm __volatile("mcr p13, 0, %0, c2, c0"
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:
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: "r" (0));
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i80200_extirq_dispatch = i80200_default_extirq_dispatch;
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}
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/*
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* i80200_intr_enable:
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*
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* Enable an interrupt source in the i80200 ICU.
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*/
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void
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i80200_intr_enable(uint32_t intr)
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{
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u_int oldirqstate;
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oldirqstate = disable_interrupts(I32_bit|F32_bit);
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intctl |= intr;
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__asm __volatile("mcr p13, 0, %0, c0, c0"
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:
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: "r" (intctl));
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restore_interrupts(oldirqstate);
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}
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/*
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* i80200_intr_disable:
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*
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* Disable an interrupt source in the i80200 ICU.
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*/
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void
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i80200_intr_disable(uint32_t intr)
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{
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u_int oldirqstate;
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oldirqstate = disable_interrupts(I32_bit|F32_bit);
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intctl &= ~intr;
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__asm __volatile("mcr p13, 0, %0, c0, c0"
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:
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: "r" (intctl));
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restore_interrupts(oldirqstate);
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}
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