653 lines
13 KiB
C
653 lines
13 KiB
C
/* $NetBSD: iomd_irqhandler.c,v 1.11 1996/11/06 18:18:41 mark Exp $ */
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/*
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* Copyright (c) 1994-1996 Mark Brinicombe.
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* Copyright (c) 1994 Brini.
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* All rights reserved.
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*
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* This code is derived from software written for Brini by Mark Brinicombe
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Brini.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* irqhandler.c
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*
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* IRQ/FIQ initialisation, claim, release and handler routines
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*
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* Created : 30/09/94
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/syslog.h>
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#include <vm/vm.h>
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#include <net/netisr.h>
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#include <machine/irqhandler.h>
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#include <machine/cpu.h>
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#include <machine/iomd.h>
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#include <machine/katelib.h>
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#include "podulebus.h"
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irqhandler_t *irqhandlers[NIRQS];
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fiqhandler_t *fiqhandlers;
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int current_intr_depth = 0;
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u_int irqmasks[IRQ_LEVELS];
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u_int current_mask;
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u_int actual_mask;
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u_int disabled_mask = 0;
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u_int spl_mask;
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u_int soft_interrupts;
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extern u_int intrcnt[];
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typedef struct {
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vm_offset_t physical;
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vm_offset_t virtual;
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} pv_addr_t;
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extern pv_addr_t systempage;
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extern char *_intrnames;
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/* Prototypes */
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int podule_irqhandler __P((void));
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int irq_claim __P((int irq, irqhandler_t *handler));
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extern void zero_page_readonly __P((void));
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extern void zero_page_readwrite __P((void));
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extern int fiq_setregs __P((fiqhandler_t *));
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extern int fiq_getregs __P((fiqhandler_t *));
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extern void set_spl_masks __P((void));
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extern void arpintr __P((void));
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extern void ipintr __P((void));
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extern void pppintr __P((void));
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extern void plipintr __P((void));
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/*
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* void irq_init(void)
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*
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* Initialise the IRQ/FIQ sub system
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*/
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void
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irq_init()
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{
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int loop;
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/* Clear all the IRQ handlers */
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for (loop = 0; loop < NIRQS; ++loop)
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irqhandlers[loop] = NULL;
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/* Clear the FIQ handler */
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fiqhandlers = NULL;
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/* Clear the IRQ/FIQ masks in the IOMD */
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WriteByte(IOMD_IRQMSKA, 0x00);
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WriteByte(IOMD_IRQMSKB, 0x00);
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#ifdef CPU_ARM7500
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WriteByte(IOMD_IRQMSKC, 0x00);
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WriteByte(IOMD_IRQMSKD, 0x00);
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#endif /* CPU_ARM7500 */
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WriteByte(IOMD_FIQMSK, 0x00);
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WriteByte(IOMD_DMAMSK, 0x00);
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/*
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* Setup the irqmasks for the different Interrupt Priority Levels
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* We will start with no bits set and these will be updated as handlers
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* are installed at different IPL's.
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*/
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irqmasks[IPL_BIO] = 0x00000000;
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irqmasks[IPL_NET] = 0x00000000;
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irqmasks[IPL_TTY] = 0x00000000;
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irqmasks[IPL_CLOCK] = 0x00000000;
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irqmasks[IPL_IMP] = 0x00000000;
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irqmasks[IPL_NONE] = 0x00000000;
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current_mask = 0x00000000;
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actual_mask = 0x00000000;
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spl_mask = 0x00000000;
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soft_interrupts = 0x00000000;
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set_spl_masks();
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/* Enable IRQ's and FIQ's */
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enable_interrupts(I32_bit | F32_bit);
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}
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/*
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* int irq_claim(int irq, irqhandler_t *handler)
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*
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* Enable an IRQ and install a handler for it.
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*/
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int
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irq_claim(irq, handler)
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int irq;
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irqhandler_t *handler;
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{
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int level;
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#ifdef DIAGNOSTIC
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/* Sanity check */
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if (handler == NULL)
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panic("NULL interrupt handler\n");
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if (handler->ih_func == NULL)
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panic("Interrupt handler does not have a function\n");
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#endif /* DIAGNOSTIC */
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/*
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* IRQ_INSTRUCT indicates that we should get the irq number
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* from the irq structure
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*/
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if (irq == IRQ_INSTRUCT)
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irq = handler->ih_num;
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/* Make sure the irq number is valid */
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if (irq < 0 || irq >= NIRQS)
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return(-1);
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/* Attach handler at top of chain */
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handler->ih_next = irqhandlers[irq];
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irqhandlers[irq] = handler;
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/*
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* Reset the flags for this handler.
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* As the handler is now in the chain mark it as active.
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*/
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handler->ih_flags = 0 | IRQ_FLAG_ACTIVE;
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/*
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* Record the interrupt number for accounting.
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* Done here as the accounting number may not be the same as the IRQ number
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* though for the moment they are
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*/
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handler->ih_num = irq;
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#ifdef IRQSTATS
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/* Get the interrupt name from the head of the list */
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if (handler->ih_name) {
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char *ptr = _intrnames + (irq * 14);
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strcpy(ptr, " ");
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strncpy(ptr, handler->ih_name,
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min(strlen(handler->ih_name), 13));
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} else {
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char *ptr = _intrnames + (irq * 14);
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sprintf(ptr, "irq %2d ", irq);
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}
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#endif /* IRQSTATS */
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/*
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* Update the irq masks.
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* Find the lowest interrupt priority on the irq chain.
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* Interrupt is allowable at priorities lower than this.
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* If ih_level is out of range then don't bother to update
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* the masks.
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*/
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if (handler->ih_level >= 0 && handler->ih_level < IRQ_LEVELS) {
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irqhandler_t *ptr;
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ptr = irqhandlers[irq];
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if (ptr) {
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level = ptr->ih_level - 1;
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while (ptr) {
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if (ptr->ih_level - 1 < level)
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level = ptr->ih_level - 1;
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ptr = ptr->ih_next;
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}
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while (level >= 0) {
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irqmasks[level] |= (1 << irq);
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--level;
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}
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}
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#include "sl.h"
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#include "ppp.h"
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#if NSL > 0 || NPPP > 0
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/* In the presence of SLIP or PPP, splimp > spltty. */
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irqmasks[IPL_NET] &= irqmasks[IPL_TTY];
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#endif
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}
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#if NPODULEBUS > 0
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/*
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* Is this an expansion card IRQ and is there a PODULE IRQ handler
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* installed ?
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* If not panic as the podulebus irq handler should have been installed
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* when the podulebus was attached.
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*
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* The podule IRQ's need to be fixed ASAP
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*/
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if (irq >= IRQ_EXPCARD0 && irqhandlers[IRQ_PODULE] == NULL)
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panic("Podule IRQ %d claimed but no podulebus handler installed\n",
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irq);
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#endif /* NPODULEBUS */
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enable_irq(irq);
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set_spl_masks();
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return(0);
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}
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/*
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* int irq_release(int irq, irqhandler_t *handler)
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*
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* Disable an IRQ and remove a handler for it.
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*/
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int
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irq_release(irq, handler)
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int irq;
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irqhandler_t *handler;
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{
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int level;
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irqhandler_t *irqhand;
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irqhandler_t **prehand;
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extern char *_intrnames;
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/*
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* IRQ_INSTRUCT indicates that we should get the irq number
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* from the irq structure
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*/
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if (irq == IRQ_INSTRUCT)
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irq = handler->ih_num;
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/* Make sure the irq number is valid */
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if (irq < 0 || irq >= NIRQS)
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return(-1);
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/* Locate the handler */
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irqhand = irqhandlers[irq];
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prehand = &irqhandlers[irq];
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while (irqhand && handler != irqhand) {
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prehand = &irqhand;
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irqhand = irqhand->ih_next;
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}
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/* Remove the handler if located */
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if (irqhand)
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*prehand = irqhand->ih_next;
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else
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return(-1);
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/* Now the handler has been removed from the chain mark is as inactive */
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irqhand->ih_flags &= ~IRQ_FLAG_ACTIVE;
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/* Make sure the head of the handler list is active */
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if (irqhandlers[irq])
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irqhandlers[irq]->ih_flags |= IRQ_FLAG_ACTIVE;
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#ifdef IRQSTATS
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/* Get the interrupt name from the head of the list */
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if (irqhandlers[irq] && irqhandlers[irq]->ih_name) {
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char *ptr = _intrnames + (irq * 14);
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strcpy(ptr, " ");
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strncpy(ptr, irqhandlers[irq]->ih_name,
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min(strlen(irqhandlers[irq]->ih_name), 13));
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} else {
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char *ptr = _intrnames + (irq * 14);
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sprintf(ptr, "irq %2d ", irq);
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}
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#endif /* IRQSTATS */
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/*
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* Update the irq masks.
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* If ih_level is out of range then don't bother to update
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* the masks.
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*/
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if (handler->ih_level >= 0 && handler->ih_level < IRQ_LEVELS) {
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irqhandler_t *ptr;
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/* Clean the bit from all the masks */
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for (level = 0; level < IRQ_LEVELS; ++level)
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irqmasks[level] &= ~(1 << irq);
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/*
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* Find the lowest interrupt priority on the irq chain.
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* Interrupt is allowable at priorities lower than this.
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*/
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ptr = irqhandlers[irq];
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if (ptr) {
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level = ptr->ih_level - 1;
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while (ptr) {
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if (ptr->ih_level - 1 < level)
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level = ptr->ih_level - 1;
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ptr = ptr->ih_next;
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}
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while (level >= 0) {
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irqmasks[level] |= (1 << irq);
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--level;
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}
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}
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}
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/*
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* Disable the appropriate mask bit if there are no handlers left for
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* this IRQ.
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*/
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if (irqhandlers[irq] == NULL)
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disable_irq(irq);
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set_spl_masks();
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return(0);
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}
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u_int
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disable_interrupts(mask)
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u_int mask;
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{
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register u_int cpsr;
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cpsr = SetCPSR(mask, mask);
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return(cpsr);
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}
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u_int
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restore_interrupts(old_cpsr)
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u_int old_cpsr;
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{
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register int mask = I32_bit | F32_bit;
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return(SetCPSR(mask, old_cpsr & mask));
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}
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u_int
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enable_interrupts(mask)
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u_int mask;
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{
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return(SetCPSR(mask, 0));
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}
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/*
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* void disable_irq(int irq)
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*
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* Disables a specific irq. The irq is removed from the master irq mask
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*/
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void
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disable_irq(irq)
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int irq;
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{
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register int oldirqstate;
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oldirqstate = disable_interrupts(I32_bit);
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current_mask &= ~(1 << irq);
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irq_setmasks();
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restore_interrupts(oldirqstate);
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}
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/*
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* void enable_irq(int irq)
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*
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* Enables a specific irq. The irq is added to the master irq mask
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* This routine should be used with caution. A handler should already
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* be installed.
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*/
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void
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enable_irq(irq)
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int irq;
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{
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register u_int oldirqstate;
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oldirqstate = disable_interrupts(I32_bit);
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current_mask |= (1 << irq);
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irq_setmasks();
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restore_interrupts(oldirqstate);
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}
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/*
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* void stray_irqhandler(u_int mask)
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*
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* Handler for stray interrupts. This gets called if a handler cannot be
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* found for an interrupt.
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*/
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void
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stray_irqhandler(mask)
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u_int mask;
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{
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static u_int stray_irqs = 0;
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if (++stray_irqs <= 8)
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log(LOG_ERR, "Stray interrupt %08x%s\n", mask,
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stray_irqs >= 8 ? ": stopped logging" : "");
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}
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/* Handle software interrupts */
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void
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dosoftints()
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{
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register u_int softints;
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int s;
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softints = soft_interrupts & spl_mask;
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if (softints == 0) return;
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s = splsoft();
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/*
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* Software clock interrupts
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*/
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if (softints & IRQMASK_SOFTCLOCK) {
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++cnt.v_soft;
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++intrcnt[IRQ_SOFTCLOCK];
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atomic_clear_bit(&soft_interrupts, IRQMASK_SOFTCLOCK);
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softclock();
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}
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#if defined(INET) && defined(PLIP) && defined(notyet)
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if (softints & IRQMASK_SOFTPLIP) {
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++cnt.v_soft;
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++intrcnt[IRQ_SOFTPLIP];
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atomic_clear_bit(&soft_interrupts, IRQMASK_SOFTPLIP);
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plipintr();
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}
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#endif
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/*
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* Network software interrupts
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*/
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if (softints & IRQMASK_SOFTNET) {
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++cnt.v_soft;
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++intrcnt[IRQ_SOFTNET];
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atomic_clear_bit(&soft_interrupts, IRQMASK_SOFTNET);
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#ifdef INET
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#include "ether.h"
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#if NETHER > 0
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if (netisr & (1 << NETISR_ARP)) {
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atomic_clear_bit(&netisr, (1 << NETISR_ARP));
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arpintr();
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}
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#endif
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if (netisr & (1 << NETISR_IP)) {
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atomic_clear_bit(&netisr, (1 << NETISR_IP));
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ipintr();
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}
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#endif
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#ifdef NS
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if (netisr & (1 << NETISR_NS)) {
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atomic_clear_bit(&netisr, (1 << NETISR_NS));
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nsintr();
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}
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#endif
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#ifdef IMP
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if (netisr & (1 << NETISR_IMP)) {
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atomic_clear_bit(&netisr, (1 << NETISR_IMP));
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impintr();
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}
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#endif
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#ifdef ISO
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if (netisr & (1 << NETISR_ISO)) {
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atomic_clear_bit(&netisr, (1 << NETISR_ISO));
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clnlintr();
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}
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#endif
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#ifdef CCITT
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if (netisr & (1 << NETISR_CCITT)) {
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atomic_clear_bit(&netisr, (1 << NETISR_CCITT));
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ccittintr();
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}
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#endif
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#include "ppp.h"
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#ifdef NPPP
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if (netisr & (1 << NETISR_PPP)) {
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atomic_clear_bit(&netisr, (1 << NETISR_PPP));
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pppintr();
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}
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#endif
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}
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(void)splx(s);
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}
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/*
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* int fiq_claim(fiqhandler_t *handler)
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*
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* Claim FIQ's and install a handler for them.
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*/
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int
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fiq_claim(handler)
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fiqhandler_t *handler;
|
|
{
|
|
/* Fail if the FIQ's are already claimed */
|
|
|
|
if (fiqhandlers)
|
|
return(-1);
|
|
|
|
if (handler->fh_size > 0xc0)
|
|
return(-1);
|
|
|
|
/* Install the handler */
|
|
|
|
fiqhandlers = handler;
|
|
|
|
/* Now we have to actually install the FIQ handler */
|
|
|
|
/* Eventually we will copy this down but for the moment ... */
|
|
|
|
zero_page_readwrite();
|
|
|
|
WriteWord(0x0000003c, (u_int) handler->fh_func);
|
|
|
|
zero_page_readonly();
|
|
|
|
/* We must now set up the FIQ registers */
|
|
|
|
fiq_setregs(handler);
|
|
|
|
/* Set up the FIQ mask */
|
|
|
|
WriteWord(IOMD_FIQMSK, handler->fh_mask);
|
|
|
|
/* Make sure that the FIQ's are enabled */
|
|
|
|
enable_interrupts(F32_bit);
|
|
return(0);
|
|
}
|
|
|
|
|
|
/*
|
|
* int fiq_release(fiqhandler_t *handler)
|
|
*
|
|
* Release FIQ's and remove a handler for them.
|
|
*/
|
|
|
|
int
|
|
fiq_release(handler)
|
|
fiqhandler_t *handler;
|
|
{
|
|
/* Fail if the handler is wrong */
|
|
|
|
if (fiqhandlers != handler)
|
|
return(-1);
|
|
|
|
/* Disable FIQ interrupts */
|
|
|
|
disable_interrupts(F32_bit);
|
|
|
|
/* Clear up the FIQ mask */
|
|
|
|
WriteWord(IOMD_FIQMSK, 0x00);
|
|
|
|
/* Retrieve the FIQ registers */
|
|
|
|
fiq_getregs(handler);
|
|
|
|
/* Remove the handler */
|
|
|
|
fiqhandlers = NULL;
|
|
return(0);
|
|
}
|
|
|
|
/* End of irqhandler.c */
|