190 lines
7.8 KiB
C
190 lines
7.8 KiB
C
/* $NetBSD: fpu_emu.h,v 1.1.1.1 1998/06/20 04:58:51 eeh Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)fpu_emu.h 8.1 (Berkeley) 6/11/93
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*/
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/*
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* Floating point emulator (tailored for SPARC, but structurally
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* machine-independent).
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*
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* Floating point numbers are carried around internally in an `expanded'
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* or `unpacked' form consisting of:
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* - sign
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* - unbiased exponent
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* - mantissa (`1.' + 112-bit fraction + guard + round)
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* - sticky bit
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* Any implied `1' bit is inserted, giving a 113-bit mantissa that is
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* always nonzero. Additional low-order `guard' and `round' bits are
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* scrunched in, making the entire mantissa 115 bits long. This is divided
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* into four 32-bit words, with `spare' bits left over in the upper part
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* of the top word (the high bits of fp_mant[0]). An internal `exploded'
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* number is thus kept within the half-open interval [1.0,2.0) (but see
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* the `number classes' below). This holds even for denormalized numbers:
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* when we explode an external denorm, we normalize it, introducing low-order
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* zero bits, so that the rest of the code always sees normalized values.
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*
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* Note that a number of our algorithms use the `spare' bits at the top.
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* The most demanding algorithm---the one for sqrt---depends on two such
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* bits, so that it can represent values up to (but not including) 8.0,
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* and then it needs a carry on top of that, so that we need three `spares'.
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*
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* The sticky-word is 32 bits so that we can use `OR' operators to goosh
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* whole words from the mantissa into it.
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*
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* All operations are done in this internal extended precision. According
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* to Hennesey & Patterson, Appendix A, rounding can be repeated---that is,
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* it is OK to do a+b in extended precision and then round the result to
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* single precision---provided single, double, and extended precisions are
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* `far enough apart' (they always are), but we will try to avoid any such
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* extra work where possible.
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*/
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struct fpn {
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int fp_class; /* see below */
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int fp_sign; /* 0 => positive, 1 => negative */
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int fp_exp; /* exponent (unbiased) */
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int fp_sticky; /* nonzero bits lost at right end */
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u_int fp_mant[4]; /* 115-bit mantissa */
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};
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#define FP_NMANT 115 /* total bits in mantissa (incl g,r) */
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#define FP_NG 2 /* number of low-order guard bits */
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#define FP_LG ((FP_NMANT - 1) & 31) /* log2(1.0) for fp_mant[0] */
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#define FP_QUIETBIT (1 << (FP_LG - 1)) /* Quiet bit in NaNs (0.5) */
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#define FP_1 (1 << FP_LG) /* 1.0 in fp_mant[0] */
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#define FP_2 (1 << (FP_LG + 1)) /* 2.0 in fp_mant[0] */
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/*
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* Number classes. Since zero, Inf, and NaN cannot be represented using
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* the above layout, we distinguish these from other numbers via a class.
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* In addition, to make computation easier and to follow Appendix N of
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* the SPARC Version 8 standard, we give each kind of NaN a separate class.
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*/
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#define FPC_SNAN -2 /* signalling NaN (sign irrelevant) */
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#define FPC_QNAN -1 /* quiet NaN (sign irrelevant) */
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#define FPC_ZERO 0 /* zero (sign matters) */
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#define FPC_NUM 1 /* number (sign matters) */
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#define FPC_INF 2 /* infinity (sign matters) */
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#define ISNAN(fp) ((fp)->fp_class < 0)
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#define ISZERO(fp) ((fp)->fp_class == 0)
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#define ISINF(fp) ((fp)->fp_class == FPC_INF)
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/*
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* ORDER(x,y) `sorts' a pair of `fpn *'s so that the right operand (y) points
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* to the `more significant' operand for our purposes. Appendix N says that
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* the result of a computation involving two numbers are:
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*
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* If both are SNaN: operand 2, converted to Quiet
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* If only one is SNaN: the SNaN operand, converted to Quiet
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* If both are QNaN: operand 2
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* If only one is QNaN: the QNaN operand
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*
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* In addition, in operations with an Inf operand, the result is usually
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* Inf. The class numbers are carefully arranged so that if
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* (unsigned)class(op1) > (unsigned)class(op2)
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* then op1 is the one we want; otherwise op2 is the one we want.
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*/
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#define ORDER(x, y) { \
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if ((u_int)(x)->fp_class > (u_int)(y)->fp_class) \
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SWAP(x, y); \
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}
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#define SWAP(x, y) { \
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register struct fpn *swap; \
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swap = (x), (x) = (y), (y) = swap; \
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}
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/*
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* Emulator state.
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*/
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struct fpemu {
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struct fpstate *fe_fpstate; /* registers, etc */
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int fe_fsr; /* fsr copy (modified during op) */
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int fe_cx; /* exceptions */
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struct fpn fe_f1; /* operand 1 */
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struct fpn fe_f2; /* operand 2, if required */
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struct fpn fe_f3; /* available storage for result */
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};
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/*
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* Arithmetic functions.
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* Each of these may modify its inputs (f1,f2) and/or the temporary.
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* Each returns a pointer to the result and/or sets exceptions.
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*/
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struct fpn *fpu_add(struct fpemu *);
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#define fpu_sub(fe) ((fe)->fe_f2.fp_sign ^= 1, fpu_add(fe))
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struct fpn *fpu_mul(struct fpemu *);
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struct fpn *fpu_div(struct fpemu *);
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struct fpn *fpu_sqrt(struct fpemu *);
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/*
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* Other functions.
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*/
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/* Perform a compare instruction (with or without unordered exception). */
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void fpu_compare(struct fpemu *, int);
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/* Build a new Quiet NaN (sign=0, frac=all 1's). */
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struct fpn *fpu_newnan(struct fpemu *);
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/*
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* Shift a number right some number of bits, taking care of round/sticky.
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* Note that the result is probably not a well-formed number (it will lack
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* the normal 1-bit mant[0]&FP_1).
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*/
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int fpu_shr(struct fpn *, int);
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/* Conversion to and from internal format -- note asymmetry. */
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int fpu_itofpn(struct fpn *, u_int);
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int fpu_stofpn(struct fpn *, u_int);
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int fpu_dtofpn(struct fpn *, u_int, u_int);
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int fpu_xtofpn(struct fpn *, u_int, u_int, u_int, u_int);
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u_int fpu_fpntoi(struct fpemu *, struct fpn *);
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u_int fpu_fpntos(struct fpemu *, struct fpn *);
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u_int fpu_fpntod(struct fpemu *, struct fpn *);
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u_int fpu_fpntox(struct fpemu *, struct fpn *);
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void fpu_explode(struct fpemu *, struct fpn *, int, int);
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void fpu_implode(struct fpemu *, struct fpn *, int, u_int *);
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