165 lines
4.9 KiB
C
165 lines
4.9 KiB
C
/* $NetBSD: gs.c,v 1.6 2014/03/31 11:25:49 martin Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gs.c,v 1.6 2014/03/31 11:25:49 martin Exp $");
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#include <sys/param.h>
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#include <playstation2/playstation2/sifbios.h>
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#include <playstation2/ee/eevar.h>
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#include <playstation2/ee/gsvar.h>
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#include <playstation2/ee/gsreg.h>
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#include <playstation2/ee/gifreg.h>
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#ifdef DEBUG
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#define STATIC
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#else
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#define STATIC static
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#endif
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STATIC const struct gs_crt_param {
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int w, h, dvemode;
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u_int64_t smode1, smode2, srfsh, synch1, synch2, syncv, display;
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} gs_crt_param[] = {
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[NTSC_NONINTER] = {
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.w = 640,
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.h = 240,
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.dvemode= 0,
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.smode1 = SMODE1(0, 1, 1, 1, 1, 0, 0, 0, 0, 0,
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4, 0, 0, 1, 1, 0, 2, 0, 1, 32, 4),
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.smode2 = SMODE2(0, 0, 0),
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.srfsh = SRFSH(8),
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.synch1 = SYNCH1(254, 1462, 124, 222, 64),
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.synch2 = SYNCH2(1652, 1240),
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.syncv = SYNCV(6, 480, 6, 26, 6, 2),
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.display=DISPLAY(239, 2559, 0, 3, 25, 632)
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},
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[NTSC_INTER] = {
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.w = 640,
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.h = 480,
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.dvemode= 0,
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.smode1 = SMODE1(0, 1, 1, 1, 1, 0, 0, 0, 0, 0,
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4, 0, 0, 1, 1, 0, 2, 0, 1, 32, 4),
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.smode2 = SMODE2(0, 0, 1),
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.srfsh = SRFSH(8),
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.synch1 = SYNCH1(254, 1462, 124, 222, 64),
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.synch2 = SYNCH2(1652, 1240),
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.syncv = SYNCV(6, 480, 6, 26, 6, 1),
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.display= DISPLAY(479, 2559, 0, 3, 50, 632)
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},
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[PAL_NONINTER] = {
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.w = 640,
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.h = 288,
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.dvemode= 1,
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.smode1 = SMODE1(0, 1, 1, 1, 1, 0, 0, 0, 0, 0,
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4, 0, 0, 1, 1, 0, 3, 0, 1, 32, 4),
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.smode2 = SMODE2(0, 0, 0),
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.srfsh = SRFSH(8),
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.synch1 = SYNCH1(254, 1474, 127, 262, 48),
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.synch2 = SYNCH2(1680, 1212),
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.syncv = SYNCV(5, 576, 5, 33, 5, 4),
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.display= DISPLAY(287, 2559, 0, 3, 36, 652)
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},
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[PAL_INTER] = {
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.w = 640,
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.h = 576,
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.dvemode= 1,
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.smode1 = SMODE1(0, 1, 1, 1, 1, 0, 0, 0, 0, 0,
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4, 0, 0, 1, 1, 0, 3, 0, 1, 32, 4),
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.smode2 = SMODE2(0, 0, 1),
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.srfsh = SRFSH(8),
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.synch1 = SYNCH1(254, 1474, 127, 262, 48),
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.synch2 = SYNCH2(1680, 1212),
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.syncv = SYNCV(5, 576, 5, 33, 5, 4),
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.display= DISPLAY(575,2559,0,3,72,652)
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},
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[VESA_1A] = {
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.w = 640,
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.h = 480,
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.dvemode= 2,
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.smode1 = SMODE1(1, 0, 1, 1, 1, 0, 0, 0, 0, 0,
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2, 0, 0, 1, 0, 0, 0, 0, 1, 15, 2),
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.smode2 = SMODE2(0, 0, 0),
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.srfsh = SRFSH(4),
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.synch1 = SYNCH1(192, 608, 192, 84, 32),
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.synch2 = SYNCH2(768, 524),
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.syncv = SYNCV(2, 480, 0, 33, 0, 10),
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.display= DISPLAY(479, 1279, 0, 1, 34, 276)
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}
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};
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void
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gs_init(enum gs_crt_type type)
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{
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const struct gs_crt_param *p = &gs_crt_param[type];
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u_int64_t smode1 = p->smode1;
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/* GS reset */
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_reg_write_8(GS_S_CSR_REG, 1 << 9);
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/* setup PCRTC */
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_reg_write_8(GS_S_PMODE_REG, 0); /* disable circuit 1/2 */
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_reg_write_8(GS_S_SMODE1_REG, smode1 | ((u_int64_t)1 << 16));
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_reg_write_8(GS_S_SYNCH1_REG, p->synch1);
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_reg_write_8(GS_S_SYNCH2_REG, p->synch2);
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_reg_write_8(GS_S_SYNCV_REG, p->syncv);
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_reg_write_8(GS_S_SMODE2_REG, p->smode2);
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_reg_write_8(GS_S_SRFSH_REG, p->srfsh);
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if (p->dvemode == 2) { /* PLL on */
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_reg_write_8(GS_S_SMODE1_REG, smode1 & ~((u_int64_t)1 << 16));
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delay(2500);
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}
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/* start sync */
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_reg_write_8(GS_S_SMODE1_REG,
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smode1 & ~((u_int64_t)1 << 16) & ~((u_int64_t)1 << 17));
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sifbios_setdve(p->dvemode);
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/* enable circuit */
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_reg_write_8(GS_S_PMODE_REG, 0x66);
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/* display environment */
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_reg_write_8(GS_S_DISPLAY2_REG, p->display);
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_reg_write_8(GS_S_DISPFB2_REG, (p->w >> 6) << 9);
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_reg_write_8(GS_S_SMODE2_REG, p->smode2);
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_reg_write_8(GS_S_BGCOLOR_REG, 0);
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/* Flush GS FIFO */
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_reg_write_8(GS_S_CSR_REG, 1 << 8);
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/* GIF reset */
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_reg_write_4(GIF_CTRL_REG, 1);
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}
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