462 lines
11 KiB
C
462 lines
11 KiB
C
/* $NetBSD: ixp425_pci_space.c,v 1.6 2006/04/10 03:36:03 simonb Exp $ */
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/*
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* Copyright (c) 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ixp425_pci_space.c,v 1.6 2006/04/10 03:36:03 simonb Exp $");
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/*
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* bus_space PCI functions for ixp425
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/queue.h>
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#include <uvm/uvm.h>
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#include <machine/bus.h>
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#include <arm/xscale/ixp425reg.h>
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#include <arm/xscale/ixp425var.h>
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/*
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* Macros to read/write registers
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*/
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#define CSR_READ_4(x) *(volatile uint32_t *) \
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(IXP425_PCI_CSR_BASE + (x))
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#define CSR_WRITE_4(x, v) *(volatile uint32_t *) \
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(IXP425_PCI_CSR_BASE + (x)) = (v)
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/* Proto types for all the bus_space structure functions */
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bs_protos(ixp425_pci);
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bs_protos(ixp425_pci_io);
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bs_protos(ixp425_pci_mem);
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bs_protos(bs_notimpl);
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/* special I/O functions */
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#if 1 /* XXX */
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inline u_int8_t _pci_io_bs_r_1(void *, bus_space_handle_t, bus_size_t);
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inline u_int16_t _pci_io_bs_r_2(void *, bus_space_handle_t, bus_size_t);
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inline u_int32_t _pci_io_bs_r_4(void *, bus_space_handle_t, bus_size_t);
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inline void _pci_io_bs_w_1(void *, bus_space_handle_t, bus_size_t, u_int8_t);
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inline void _pci_io_bs_w_2(void *, bus_space_handle_t, bus_size_t, u_int16_t);
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inline void _pci_io_bs_w_4(void *, bus_space_handle_t, bus_size_t, u_int32_t);
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#endif
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struct bus_space ixp425_pci_bs_tag_template = {
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/* cookie */
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(void *) 0,
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/* mapping/unmapping */
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NULL,
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NULL,
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ixp425_pci_bs_subregion,
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/* allocation/deallocation */
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NULL,
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NULL,
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/* get kernel virtual address */
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NULL,
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/* mmap bus space for userland */
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ixp425_pci_bs_mmap,
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/* barrier */
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ixp425_pci_bs_barrier,
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/* read (single) */
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bs_notimpl_bs_r_1,
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bs_notimpl_bs_r_2,
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bs_notimpl_bs_r_4,
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bs_notimpl_bs_r_8,
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/* read multiple */
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bs_notimpl_bs_rm_1,
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bs_notimpl_bs_rm_2,
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bs_notimpl_bs_rm_4,
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bs_notimpl_bs_rm_8,
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/* read region */
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bs_notimpl_bs_rr_1,
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bs_notimpl_bs_rr_2,
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bs_notimpl_bs_rr_4,
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bs_notimpl_bs_rr_8,
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/* write (single) */
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bs_notimpl_bs_w_1,
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bs_notimpl_bs_w_2,
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bs_notimpl_bs_w_4,
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bs_notimpl_bs_w_8,
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/* write multiple */
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bs_notimpl_bs_wm_1,
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bs_notimpl_bs_wm_2,
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bs_notimpl_bs_wm_4,
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bs_notimpl_bs_wm_8,
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/* write region */
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bs_notimpl_bs_wr_1,
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bs_notimpl_bs_wr_2,
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bs_notimpl_bs_wr_4,
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bs_notimpl_bs_wr_8,
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/* set multiple */
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bs_notimpl_bs_sm_1,
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bs_notimpl_bs_sm_2,
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bs_notimpl_bs_sm_4,
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bs_notimpl_bs_sm_8,
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/* set region */
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bs_notimpl_bs_sr_1,
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bs_notimpl_bs_sr_2,
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bs_notimpl_bs_sr_4,
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bs_notimpl_bs_sr_8,
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/* copy */
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bs_notimpl_bs_c_1,
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bs_notimpl_bs_c_2,
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bs_notimpl_bs_c_4,
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bs_notimpl_bs_c_8,
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};
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void
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ixp425_io_bs_init(bus_space_tag_t bs, void *cookie)
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{
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*bs = ixp425_pci_bs_tag_template;
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bs->bs_cookie = cookie;
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bs->bs_map = ixp425_pci_io_bs_map;
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bs->bs_unmap = ixp425_pci_io_bs_unmap;
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bs->bs_alloc = ixp425_pci_io_bs_alloc;
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bs->bs_free = ixp425_pci_io_bs_free;
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bs->bs_vaddr = ixp425_pci_io_bs_vaddr;
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/*
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* IXP425 processor does not have PCI I/O windows
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*/
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/* read (single) */
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bs->bs_r_1 = _pci_io_bs_r_1;
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bs->bs_r_2 = _pci_io_bs_r_2;
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bs->bs_r_4 = _pci_io_bs_r_4;
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/* write (single) */
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bs->bs_w_1 = _pci_io_bs_w_1;
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bs->bs_w_2 = _pci_io_bs_w_2;
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bs->bs_w_4 = _pci_io_bs_w_4;
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}
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void
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ixp425_mem_bs_init(bus_space_tag_t bs, void *cookie)
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{
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*bs = ixp425_pci_bs_tag_template;
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bs->bs_cookie = cookie;
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bs->bs_map = ixp425_pci_mem_bs_map;
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bs->bs_unmap = ixp425_pci_mem_bs_unmap;
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bs->bs_alloc = ixp425_pci_mem_bs_alloc;
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bs->bs_free = ixp425_pci_mem_bs_free;
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bs->bs_vaddr = ixp425_pci_mem_bs_vaddr;
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/* read (single) */
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bs->bs_r_1 = ixp425_pci_mem_bs_r_1;
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bs->bs_r_2 = ixp425_pci_mem_bs_r_2;
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bs->bs_r_4 = ixp425_pci_mem_bs_r_4;
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/* write (single) */
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bs->bs_w_1 = ixp425_pci_mem_bs_w_1;
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bs->bs_w_2 = ixp425_pci_mem_bs_w_2;
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bs->bs_w_4 = ixp425_pci_mem_bs_w_4;
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}
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/* common routine */
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int
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ixp425_pci_bs_subregion(void *t, bus_space_handle_t bsh, bus_size_t offset,
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bus_size_t size, bus_space_handle_t *nbshp)
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{
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*nbshp = bsh + offset;
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return (0);
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}
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void
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ixp425_pci_bs_barrier(void *t, bus_space_handle_t bsh, bus_size_t offset,
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bus_size_t len, int flags)
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{
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/* NULL */
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}
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paddr_t
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ixp425_pci_bs_mmap(void *t, bus_addr_t addr, off_t off, int prot, int flags)
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{
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/* Not supported. */
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return (-1);
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}
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/* io bs */
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int
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ixp425_pci_io_bs_map(void *t, bus_addr_t bpa, bus_size_t size,
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int cacheable, bus_space_handle_t *bshp)
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{
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*bshp = bpa;
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return (0);
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}
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void
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ixp425_pci_io_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
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{
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/* Nothing to do. */
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}
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int
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ixp425_pci_io_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
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bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
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bus_addr_t *bpap, bus_space_handle_t *bshp)
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{
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panic("ixp425_pci_io_bs_alloc(): not implemented\n");
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}
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void
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ixp425_pci_io_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
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{
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panic("ixp425_pci_io_bs_free(): not implemented\n");
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}
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void *
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ixp425_pci_io_bs_vaddr(void *t, bus_space_handle_t bsh)
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{
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/* Not supported. */
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return (NULL);
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}
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/* special I/O functions */
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#if 1 /* _pci_io_bs_{rw}_{124} */
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inline u_int8_t
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_pci_io_bs_r_1(void *v, bus_space_handle_t ioh, bus_size_t off)
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{
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u_int32_t data, n, be;
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int s;
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n = (ioh + off) % 4;
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be = (0xf & ~(1U << n)) << NP_CBE_SHIFT;
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PCI_CONF_LOCK(s);
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CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
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CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ);
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data = CSR_READ_4(PCI_NP_RDATA);
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if (CSR_READ_4(PCI_ISR) & ISR_PFE)
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CSR_WRITE_4(PCI_ISR, ISR_PFE);
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PCI_CONF_UNLOCK(s);
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return data >> (8 * n);
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}
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inline u_int16_t
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_pci_io_bs_r_2(void *v, bus_space_handle_t ioh, bus_size_t off)
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{
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u_int32_t data, n, be;
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int s;
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n = (ioh + off) % 4;
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be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT;
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PCI_CONF_LOCK(s);
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CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
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CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_READ);
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data = CSR_READ_4(PCI_NP_RDATA);
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if (CSR_READ_4(PCI_ISR) & ISR_PFE)
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CSR_WRITE_4(PCI_ISR, ISR_PFE);
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PCI_CONF_UNLOCK(s);
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return data >> (8 * n);
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}
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inline u_int32_t
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_pci_io_bs_r_4(void *v, bus_space_handle_t ioh, bus_size_t off)
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{
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u_int32_t data;
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int s;
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PCI_CONF_LOCK(s);
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CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
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CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_READ);
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data = CSR_READ_4(PCI_NP_RDATA);
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if (CSR_READ_4(PCI_ISR) & ISR_PFE)
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CSR_WRITE_4(PCI_ISR, ISR_PFE);
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PCI_CONF_UNLOCK(s);
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return data;
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}
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inline void
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_pci_io_bs_w_1(void *v, bus_space_handle_t ioh, bus_size_t off,
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u_int8_t val)
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{
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u_int32_t data, n, be;
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int s;
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n = (ioh + off) % 4;
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be = (0xf & ~(1U << n)) << NP_CBE_SHIFT;
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data = val << (8 * n);
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PCI_CONF_LOCK(s);
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CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
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CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE);
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CSR_WRITE_4(PCI_NP_WDATA, data);
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if (CSR_READ_4(PCI_ISR) & ISR_PFE)
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CSR_WRITE_4(PCI_ISR, ISR_PFE);
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PCI_CONF_UNLOCK(s);
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}
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inline void
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_pci_io_bs_w_2(void *v, bus_space_handle_t ioh, bus_size_t off,
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u_int16_t val)
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{
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u_int32_t data, n, be;
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int s;
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n = (ioh + off) % 4;
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be = (0xf & ~((1U << n) | (1U << (n + 1)))) << NP_CBE_SHIFT;
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data = val << (8 * n);
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PCI_CONF_LOCK(s);
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CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
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CSR_WRITE_4(PCI_NP_CBE, be | COMMAND_NP_IO_WRITE);
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CSR_WRITE_4(PCI_NP_WDATA, data);
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if (CSR_READ_4(PCI_ISR) & ISR_PFE)
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CSR_WRITE_4(PCI_ISR, ISR_PFE);
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PCI_CONF_UNLOCK(s);
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}
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inline void
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_pci_io_bs_w_4(void *v, bus_space_handle_t ioh, bus_size_t off,
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u_int32_t val)
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{
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int s;
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PCI_CONF_LOCK(s);
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CSR_WRITE_4(PCI_NP_AD, (ioh + off) & ~3);
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CSR_WRITE_4(PCI_NP_CBE, COMMAND_NP_IO_WRITE);
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CSR_WRITE_4(PCI_NP_WDATA, val);
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if (CSR_READ_4(PCI_ISR) & ISR_PFE)
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CSR_WRITE_4(PCI_ISR, ISR_PFE);
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PCI_CONF_UNLOCK(s);
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}
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#endif /* _pci_io_bs_{rw}_{124} */
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/* mem bs */
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int
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ixp425_pci_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size,
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int cacheable, bus_space_handle_t *bshp)
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{
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const struct pmap_devmap *pd;
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paddr_t startpa;
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paddr_t endpa;
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paddr_t pa;
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paddr_t offset;
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vaddr_t va;
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pt_entry_t *pte;
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if ((pd = pmap_devmap_find_pa(bpa, size)) != NULL) {
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/* Device was statically mapped. */
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*bshp = pd->pd_va + (bpa - pd->pd_pa);
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return 0;
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}
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endpa = round_page(bpa + size);
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offset = bpa & PAGE_MASK;
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startpa = trunc_page(bpa);
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/* Get some VM. */
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va = uvm_km_alloc(kernel_map, endpa - startpa, 0,
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UVM_KMF_VAONLY | UVM_KMF_NOWAIT);
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if (va == 0)
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return ENOMEM;
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/* Store the bus space handle */
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*bshp = va + offset;
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/* Now map the pages */
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for (pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
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pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE);
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pte = vtopte(va);
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*pte &= ~L2_S_CACHE_MASK;
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PTE_SYNC(pte);
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}
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pmap_update(pmap_kernel());
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return(0);
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}
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void
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ixp425_pci_mem_bs_unmap(void *t, bus_space_handle_t bsh, bus_size_t size)
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{
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vaddr_t va;
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vaddr_t endva;
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if (pmap_devmap_find_va(bsh, size) != NULL) {
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/* Device was statically mapped; nothing to do. */
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return;
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}
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endva = round_page(bsh + size);
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va = trunc_page(bsh);
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pmap_kremove(va, endva - va);
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uvm_km_free(kernel_map, va, endva - va, UVM_KMF_VAONLY);
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}
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int
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ixp425_pci_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
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bus_size_t size, bus_size_t alignment, bus_size_t boundary, int cacheable,
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bus_addr_t *bpap, bus_space_handle_t *bshp)
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{
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panic("ixp425_mem_bs_alloc(): not implemented\n");
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}
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void
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ixp425_pci_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
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{
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panic("ixp425_mem_bs_free(): not implemented\n");
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}
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void *
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ixp425_pci_mem_bs_vaddr(void *t, bus_space_handle_t bsh)
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{
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return ((void *)bsh);
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}
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/* End of ixp425_pci_space.c */
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