121 lines
4.2 KiB
C
121 lines
4.2 KiB
C
/* $NetBSD: s3c2400reg.h,v 1.4 2005/12/11 12:16:51 christos Exp $ */
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/*
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* Copyright (c) 2002, 2003 Genetec corp. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec corp.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Genetec corporation may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Samsung S3C2400 processor is ARM920T based integrated CPU
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*
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* Reference:
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* S3C2400X User's Manual
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*/
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#ifndef _ARM_S3C2400_S3C24X0REG_H_
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#define _ARM_S3C2400_S3C24X0REG_H_
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/* common definitions for S3C2800, S3C2400X and S3C2410X */
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#include <arm/s3c2xx0/s3c2xx0reg.h>
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/*
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* Memory Map
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*/
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#define S3C2400_BANK_START(n) (0x02000000*(n))
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#define S3C2400_SDRAM_START S3C2400_BANK_START(6)
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#define S3C2400_AHB_START 0x14000000
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#define S3C2400_APB_START 0x15000000
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/*
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* Physical address of integrated peripherals
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*/
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#define S3C2400_MEMCTL_BASE 0x14000000 /* memory controller */
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#define S3C2400_USBHC_BASE 0x14200000 /* USB Host controller */
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#define S3C2400_INTCTL_BASE 0x14400000 /* Interrupt controller */
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#define S3C2400_INTCTL_SIZE 0x18
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#define S3C2400_DMAC_BASE 0x14600000 /* DMA controllers */
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#define S3C2400_DMAC_SIZE 0x80
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#define S3C2400_CLKMAN_BASE 0x14800000 /* clock & power management */
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#define S3C2400_CLKMAN_SIZE 0x18
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#define S3C2400_LCDC_BASE 0x14a00000
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#define S3C2400_UART_BASE 0x15000000
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#define S3C2400_UART_BASE(n) (S3C2400_UART_BASE+0x4000*(n))
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#define S3C2400_TIMER_BASE 0x15100000 /* Timers */
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#define S3C2400_USBDC_BASE 0x15200000 /* USB Device controller */
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#define S3C2400_USBDC_SIZE 0x1fc
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#define S3C2400_WDT_BASE 0x15300000 /* Watch dog timer */
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#define S3C2400_IIC_BASE 0x15400000
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#define S3C2400_IIS_BASE 0x15508000
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#define S3C2400_GPIO_BASE 0x15600000
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#define S3C2400_GPIO_SIZE 0x5c
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#define S3C2400_RTC_BASE 0x15700040
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#define S3C2400_RTC_SIZE 0x4c
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#define S3C2400_ADC_BASE 0x15800000 /* A/D converter */
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#define S3C2400_ADC_SIZE 0x08
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#define S3C2400_SPI_BASE 0x15900000
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#define S3C2400_MMC_BASE 0x15a00000
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#define S3C2400_MMC_SIZE 0x40
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/* GPIO */
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#define GPIO_PACON 0x00 /* port A configuration */
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#define PCON_INPUT 0 /* Input port */
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#define PCON_OUTPUT 1 /* Output port */
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#define PCON_ALTFUN 2 /* Alternate function */
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#define GPIO_PADAT 0x04 /* port A data */
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#define GPIO_PBCON 0x08
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#define GPIO_PBDAT 0x0c
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#define GPIO_PBUP 0x10
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#define GPIO_PCCON 0x14
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#define GPIO_PCDAT 0x18
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#define GPIO_PCUP 0x1c
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#define GPIO_PDCON 0x20
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#define GPIO_PDDAT 0x24
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#define GPIO_PDUP 0x28
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#define GPIO_PECON 0x3c
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#define GPIO_PEDAT 0x30
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#define GPIO_PEUP 0x34
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#define GPIO_PFCON 0x38
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#define GPIO_PFDAT 0x3c
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#define GPIO_PFUP 0x40
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#define GPIO_PGCON 0x44
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#define GPIO_PGDAT 0x49
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#define GPIO_PGUP 0x4c
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#define GPIO_OPENCR 0x50 /* Open drain enable */
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#define GPIO_MISCCR 0x54 /* miscellaneous control */
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#define GPIO_EXTINTR 0x48 /* external interrupt control */
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#define EXTINTR_LOW 0x00
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#define EXTINTR_HIGH 0x01
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#define EXTINTR_FALLING 0x02
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#define EXTINTR_RISING 0x04
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#define EXTINTR_BOTH 0x06
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/* MMC */ /* XXX */
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#endif /* _ARM_S3C2400_S3C2400REG_H_ */
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