647 lines
16 KiB
C
647 lines
16 KiB
C
/* $NetBSD: sio_pic.c,v 1.34 2005/12/11 12:16:17 christos Exp $ */
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/*-
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* Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: sio_pic.c,v 1.34 2005/12/11 12:16:17 christos Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/syslog.h>
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#include <machine/intr.h>
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#include <machine/bus.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/cy82c693reg.h>
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#include <dev/pci/cy82c693var.h>
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#include <dev/isa/isareg.h>
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#include <dev/isa/isavar.h>
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#include <alpha/pci/siovar.h>
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#include "sio.h"
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/*
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* To add to the long history of wonderful PROM console traits,
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* AlphaStation PROMs don't reset themselves completely on boot!
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* Therefore, if an interrupt was turned on when the kernel was
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* started, we're not going to EVER turn it off... I don't know
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* what will happen if new interrupts (that the PROM console doesn't
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* want) are turned on. I'll burn that bridge when I come to it.
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*/
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#define BROKEN_PROM_CONSOLE
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/*
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* Private functions and variables.
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*/
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bus_space_tag_t sio_iot;
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pci_chipset_tag_t sio_pc;
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bus_space_handle_t sio_ioh_icu1, sio_ioh_icu2;
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#define ICU_LEN 16 /* number of ISA IRQs */
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static struct alpha_shared_intr *sio_intr;
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#ifndef STRAY_MAX
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#define STRAY_MAX 5
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#endif
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#ifdef BROKEN_PROM_CONSOLE
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/*
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* If prom console is broken, must remember the initial interrupt
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* settings and enforce them. WHEE!
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*/
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u_int8_t initial_ocw1[2];
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u_int8_t initial_elcr[2];
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#endif
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void sio_setirqstat __P((int, int, int));
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u_int8_t (*sio_read_elcr) __P((int));
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void (*sio_write_elcr) __P((int, u_int8_t));
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static void specific_eoi __P((int));
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#ifdef BROKEN_PROM_CONSOLE
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void sio_intr_shutdown __P((void *));
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#endif
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/******************** i82378 SIO ELCR functions ********************/
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int i82378_setup_elcr __P((void));
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u_int8_t i82378_read_elcr __P((int));
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void i82378_write_elcr __P((int, u_int8_t));
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bus_space_handle_t sio_ioh_elcr;
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int
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i82378_setup_elcr()
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{
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int rv;
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/*
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* We could probe configuration space to see that there's
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* actually an SIO present, but we are using this as a
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* fall-back in case nothing else matches.
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*/
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rv = bus_space_map(sio_iot, 0x4d0, 2, 0, &sio_ioh_elcr);
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if (rv == 0) {
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sio_read_elcr = i82378_read_elcr;
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sio_write_elcr = i82378_write_elcr;
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}
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return (rv);
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}
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u_int8_t
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i82378_read_elcr(elcr)
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int elcr;
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{
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return (bus_space_read_1(sio_iot, sio_ioh_elcr, elcr));
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}
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void
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i82378_write_elcr(elcr, val)
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int elcr;
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u_int8_t val;
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{
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bus_space_write_1(sio_iot, sio_ioh_elcr, elcr, val);
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}
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/******************** Cypress CY82C693 ELCR functions ********************/
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int cy82c693_setup_elcr __P((void));
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u_int8_t cy82c693_read_elcr __P((int));
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void cy82c693_write_elcr __P((int, u_int8_t));
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const struct cy82c693_handle *sio_cy82c693_handle;
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int
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cy82c693_setup_elcr()
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{
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int device, maxndevs;
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pcitag_t tag;
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pcireg_t id;
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/*
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* Search PCI configuration space for a Cypress CY82C693.
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*
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* Note we can make some assumptions about our bus number
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* here, because:
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*
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* (1) there can be at most one ISA/EISA bridge per PCI bus, and
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*
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* (2) any ISA/EISA bridges must be attached to primary PCI
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* busses (i.e. bus zero).
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*/
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maxndevs = pci_bus_maxdevs(sio_pc, 0);
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for (device = 0; device < maxndevs; device++) {
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tag = pci_make_tag(sio_pc, 0, device, 0);
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id = pci_conf_read(sio_pc, tag, PCI_ID_REG);
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/* Invalid vendor ID value? */
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if (PCI_VENDOR(id) == PCI_VENDOR_INVALID)
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continue;
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/* XXX Not invalid, but we've done this ~forever. */
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if (PCI_VENDOR(id) == 0)
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continue;
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if (PCI_VENDOR(id) != PCI_VENDOR_CONTAQ ||
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PCI_PRODUCT(id) != PCI_PRODUCT_CONTAQ_82C693)
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continue;
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/*
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* Found one!
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*/
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#if 0
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printf("cy82c693_setup_elcr: found 82C693 at device %d\n",
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device);
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#endif
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sio_cy82c693_handle = cy82c693_init(sio_iot);
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sio_read_elcr = cy82c693_read_elcr;
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sio_write_elcr = cy82c693_write_elcr;
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return (0);
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}
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/*
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* Didn't find a CY82C693.
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*/
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return (ENODEV);
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}
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u_int8_t
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cy82c693_read_elcr(elcr)
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int elcr;
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{
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return (cy82c693_read(sio_cy82c693_handle, CONFIG_ELCR1 + elcr));
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}
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void
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cy82c693_write_elcr(elcr, val)
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int elcr;
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u_int8_t val;
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{
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cy82c693_write(sio_cy82c693_handle, CONFIG_ELCR1 + elcr, val);
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}
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/******************** ELCR access function configuration ********************/
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/*
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* Put the Intel SIO at the end, so we fall back on it if we don't
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* find anything else. If any of the non-Intel functions find a
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* matching device, but are unable to map it for whatever reason,
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* they should panic.
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*/
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int (*sio_elcr_setup_funcs[]) __P((void)) = {
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cy82c693_setup_elcr,
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i82378_setup_elcr,
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NULL,
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};
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/******************** Shared SIO/Cypress functions ********************/
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void
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sio_setirqstat(irq, enabled, type)
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int irq, enabled;
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int type;
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{
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u_int8_t ocw1[2], elcr[2];
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int icu, bit;
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#if 0
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printf("sio_setirqstat: irq %d: %s, %s\n", irq,
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enabled ? "enabled" : "disabled", isa_intr_typename(type));
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#endif
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icu = irq / 8;
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bit = irq % 8;
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ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1);
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ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1);
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elcr[0] = (*sio_read_elcr)(0); /* XXX */
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elcr[1] = (*sio_read_elcr)(1); /* XXX */
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/*
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* interrupt enable: set bit to mask (disable) interrupt.
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*/
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if (enabled)
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ocw1[icu] &= ~(1 << bit);
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else
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ocw1[icu] |= 1 << bit;
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/*
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* interrupt type select: set bit to get level-triggered.
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*/
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if (type == IST_LEVEL)
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elcr[icu] |= 1 << bit;
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else
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elcr[icu] &= ~(1 << bit);
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#ifdef not_here
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/* see the init function... */
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ocw1[0] &= ~0x04; /* always enable IRQ2 on first PIC */
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elcr[0] &= ~0x07; /* IRQ[0-2] must be edge-triggered */
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elcr[1] &= ~0x21; /* IRQ[13,8] must be edge-triggered */
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#endif
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bus_space_write_1(sio_iot, sio_ioh_icu1, 1, ocw1[0]);
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bus_space_write_1(sio_iot, sio_ioh_icu2, 1, ocw1[1]);
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(*sio_write_elcr)(0, elcr[0]); /* XXX */
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(*sio_write_elcr)(1, elcr[1]); /* XXX */
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}
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void
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sio_intr_setup(pc, iot)
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pci_chipset_tag_t pc;
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bus_space_tag_t iot;
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{
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char *cp;
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int i;
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sio_iot = iot;
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sio_pc = pc;
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if (bus_space_map(sio_iot, IO_ICU1, 2, 0, &sio_ioh_icu1) ||
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bus_space_map(sio_iot, IO_ICU2, 2, 0, &sio_ioh_icu2))
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panic("sio_intr_setup: can't map ICU I/O ports");
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for (i = 0; sio_elcr_setup_funcs[i] != NULL; i++)
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if ((*sio_elcr_setup_funcs[i])() == 0)
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break;
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if (sio_elcr_setup_funcs[i] == NULL)
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panic("sio_intr_setup: can't map ELCR");
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#ifdef BROKEN_PROM_CONSOLE
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/*
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* Remember the initial values, so we can restore them later.
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*/
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initial_ocw1[0] = bus_space_read_1(sio_iot, sio_ioh_icu1, 1);
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initial_ocw1[1] = bus_space_read_1(sio_iot, sio_ioh_icu2, 1);
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initial_elcr[0] = (*sio_read_elcr)(0); /* XXX */
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initial_elcr[1] = (*sio_read_elcr)(1); /* XXX */
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shutdownhook_establish(sio_intr_shutdown, 0);
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#endif
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sio_intr = alpha_shared_intr_alloc(ICU_LEN, 8);
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/*
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* set up initial values for interrupt enables.
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*/
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for (i = 0; i < ICU_LEN; i++) {
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alpha_shared_intr_set_maxstrays(sio_intr, i, STRAY_MAX);
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cp = alpha_shared_intr_string(sio_intr, i);
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sprintf(cp, "irq %d", i);
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evcnt_attach_dynamic(alpha_shared_intr_evcnt(sio_intr, i),
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EVCNT_TYPE_INTR, NULL, "isa", cp);
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switch (i) {
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case 0:
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case 1:
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case 8:
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case 13:
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/*
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* IRQs 0, 1, 8, and 13 must always be
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* edge-triggered.
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*/
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sio_setirqstat(i, 0, IST_EDGE);
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alpha_shared_intr_set_dfltsharetype(sio_intr, i,
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IST_EDGE);
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specific_eoi(i);
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break;
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case 2:
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/*
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* IRQ 2 must be edge-triggered, and should be
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* enabled (otherwise IRQs 8-15 are ignored).
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*/
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sio_setirqstat(i, 1, IST_EDGE);
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alpha_shared_intr_set_dfltsharetype(sio_intr, i,
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IST_UNUSABLE);
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break;
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default:
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/*
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* Otherwise, disable the IRQ and set its
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* type to (effectively) "unknown."
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*/
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sio_setirqstat(i, 0, IST_NONE);
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alpha_shared_intr_set_dfltsharetype(sio_intr, i,
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IST_NONE);
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specific_eoi(i);
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break;
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}
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}
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}
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#ifdef BROKEN_PROM_CONSOLE
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void
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sio_intr_shutdown(arg)
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void *arg;
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{
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/*
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* Restore the initial values, to make the PROM happy.
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*/
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bus_space_write_1(sio_iot, sio_ioh_icu1, 1, initial_ocw1[0]);
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bus_space_write_1(sio_iot, sio_ioh_icu2, 1, initial_ocw1[1]);
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(*sio_write_elcr)(0, initial_elcr[0]); /* XXX */
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(*sio_write_elcr)(1, initial_elcr[1]); /* XXX */
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}
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#endif
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const char *
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sio_intr_string(v, irq)
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void *v;
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int irq;
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{
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static char irqstr[12]; /* 8 + 2 + NULL + sanity */
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if (irq == 0 || irq >= ICU_LEN || irq == 2)
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panic("sio_intr_string: bogus isa irq 0x%x", irq);
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sprintf(irqstr, "isa irq %d", irq);
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return (irqstr);
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}
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const struct evcnt *
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sio_intr_evcnt(v, irq)
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void *v;
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int irq;
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{
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if (irq == 0 || irq >= ICU_LEN || irq == 2)
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panic("sio_intr_evcnt: bogus isa irq 0x%x", irq);
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return (alpha_shared_intr_evcnt(sio_intr, irq));
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}
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void *
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sio_intr_establish(v, irq, type, level, fn, arg)
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void *v, *arg;
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int irq;
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int type;
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int level;
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int (*fn)(void *);
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{
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void *cookie;
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if (irq > ICU_LEN || type == IST_NONE)
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panic("sio_intr_establish: bogus irq or type");
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cookie = alpha_shared_intr_establish(sio_intr, irq, type, level, fn,
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arg, "isa irq");
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if (cookie != NULL &&
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alpha_shared_intr_firstactive(sio_intr, irq)) {
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scb_set(0x800 + SCB_IDXTOVEC(irq), sio_iointr, NULL);
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sio_setirqstat(irq, 1,
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alpha_shared_intr_get_sharetype(sio_intr, irq));
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}
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return (cookie);
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}
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void
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sio_intr_disestablish(v, cookie)
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void *v;
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void *cookie;
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{
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struct alpha_shared_intrhand *ih = cookie;
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int s, ist, irq = ih->ih_num;
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s = splhigh();
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/* Remove it from the link. */
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alpha_shared_intr_disestablish(sio_intr, cookie, "isa irq");
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/*
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* Decide if we should disable the interrupt. We must ensure
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* that:
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*
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* - An initially-enabled interrupt is never disabled.
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* - An initially-LT interrupt is never untyped.
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*/
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if (alpha_shared_intr_isactive(sio_intr, irq) == 0) {
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/*
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* IRQs 0, 1, 8, and 13 must always be edge-triggered
|
|
* (see setup).
|
|
*/
|
|
switch (irq) {
|
|
case 0:
|
|
case 1:
|
|
case 8:
|
|
case 13:
|
|
/*
|
|
* If the interrupt was initially level-triggered
|
|
* a warning was printed in setup.
|
|
*/
|
|
ist = IST_EDGE;
|
|
break;
|
|
|
|
default:
|
|
ist = IST_NONE;
|
|
break;
|
|
}
|
|
sio_setirqstat(irq, 0, ist);
|
|
alpha_shared_intr_set_dfltsharetype(sio_intr, irq, ist);
|
|
|
|
/* Release our SCB vector. */
|
|
scb_free(0x800 + SCB_IDXTOVEC(irq));
|
|
}
|
|
|
|
splx(s);
|
|
}
|
|
|
|
void
|
|
sio_iointr(arg, vec)
|
|
void *arg;
|
|
unsigned long vec;
|
|
{
|
|
int irq;
|
|
|
|
irq = SCB_VECTOIDX(vec - 0x800);
|
|
|
|
#ifdef DIAGNOSTIC
|
|
if (irq > ICU_LEN || irq < 0)
|
|
panic("sio_iointr: irq out of range (%d)", irq);
|
|
#endif
|
|
|
|
if (!alpha_shared_intr_dispatch(sio_intr, irq))
|
|
alpha_shared_intr_stray(sio_intr, irq, "isa irq");
|
|
else
|
|
alpha_shared_intr_reset_strays(sio_intr, irq);
|
|
|
|
/*
|
|
* Some versions of the machines which use the SIO
|
|
* (or is it some PALcode revisions on those machines?)
|
|
* require the non-specific EOI to be fed to the PIC(s)
|
|
* by the interrupt handler.
|
|
*/
|
|
specific_eoi(irq);
|
|
}
|
|
|
|
#define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2)
|
|
|
|
int
|
|
sio_intr_alloc(v, mask, type, irq)
|
|
void *v;
|
|
int mask;
|
|
int type;
|
|
int *irq;
|
|
{
|
|
int i, tmp, bestirq, count;
|
|
struct alpha_shared_intrhand **p, *q;
|
|
|
|
if (type == IST_NONE)
|
|
panic("intr_alloc: bogus type");
|
|
|
|
bestirq = -1;
|
|
count = -1;
|
|
|
|
/* some interrupts should never be dynamically allocated */
|
|
mask &= 0xdef8;
|
|
|
|
/*
|
|
* XXX some interrupts will be used later (6 for fdc, 12 for pms).
|
|
* the right answer is to do "breadth-first" searching of devices.
|
|
*/
|
|
mask &= 0xefbf;
|
|
|
|
for (i = 0; i < ICU_LEN; i++) {
|
|
if (LEGAL_IRQ(i) == 0 || (mask & (1<<i)) == 0)
|
|
continue;
|
|
|
|
switch(sio_intr[i].intr_sharetype) {
|
|
case IST_NONE:
|
|
/*
|
|
* if nothing's using the irq, just return it
|
|
*/
|
|
*irq = i;
|
|
return (0);
|
|
|
|
case IST_EDGE:
|
|
case IST_LEVEL:
|
|
if (type != sio_intr[i].intr_sharetype)
|
|
continue;
|
|
/*
|
|
* if the irq is shareable, count the number of other
|
|
* handlers, and if it's smaller than the last irq like
|
|
* this, remember it
|
|
*
|
|
* XXX We should probably also consider the
|
|
* interrupt level and stick IPL_TTY with other
|
|
* IPL_TTY, etc.
|
|
*/
|
|
for (p = &TAILQ_FIRST(&sio_intr[i].intr_q), tmp = 0;
|
|
(q = *p) != NULL; p = &TAILQ_NEXT(q, ih_q), tmp++)
|
|
;
|
|
if ((bestirq == -1) || (count > tmp)) {
|
|
bestirq = i;
|
|
count = tmp;
|
|
}
|
|
break;
|
|
|
|
case IST_PULSE:
|
|
/* this just isn't shareable */
|
|
continue;
|
|
}
|
|
}
|
|
|
|
if (bestirq == -1)
|
|
return (1);
|
|
|
|
*irq = bestirq;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
specific_eoi(irq)
|
|
int irq;
|
|
{
|
|
if (irq > 7)
|
|
bus_space_write_1(sio_iot,
|
|
sio_ioh_icu2, 0, 0x60 | (irq & 0x07)); /* XXX */
|
|
bus_space_write_1(sio_iot, sio_ioh_icu1, 0, 0x60 | (irq > 7 ? 2 : irq));
|
|
}
|