351 lines
11 KiB
C
351 lines
11 KiB
C
/* $NetBSD: if_rtw_pci.c,v 1.20 2011/07/26 20:51:24 dyoung Exp $ */
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/*-
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* Copyright (c) 2004, 2005, 2010 David Young. All rights reserved.
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*
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* Adapted for the RTL8180 by David Young.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David
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* Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 1998, 1999, 2000, 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center; Charles M. Hannum; and David Young.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCI bus front-end for the Realtek RTL8180 802.11 MAC/BBP chip.
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*
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* Derived from the ADMtek ADM8211 PCI bus front-end.
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*
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* Derived from the ``Tulip'' PCI bus front-end.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_rtw_pci.c,v 1.20 2011/07/26 20:51:24 dyoung Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/ioctl.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <machine/endian.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_ether.h>
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#include <net80211/ieee80211_netbsd.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <net80211/ieee80211_var.h>
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#include <sys/bus.h>
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#include <sys/intr.h>
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#include <dev/ic/rtwreg.h>
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#include <dev/ic/rtwvar.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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/*
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* PCI configuration space registers used by the RTL8180.
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*/
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#define RTW_PCI_IOBA PCI_BAR(0) /* i/o mapped base */
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#define RTW_PCI_MMBA PCI_BAR(1) /* memory mapped base */
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struct rtw_pci_softc {
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struct rtw_softc psc_rtw;
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pcireg_t psc_csr;
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void *psc_ih;
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pci_chipset_tag_t psc_pc;
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pci_intr_handle_t psc_pih;
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pcitag_t psc_tag;
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};
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static void rtw_pci_attach(device_t, device_t, void *);
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static int rtw_pci_detach(device_t, int);
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#if 0
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static void rtw_pci_funcregen(struct rtw_regs *, int);
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#endif
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static const struct rtw_pci_product *
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rtw_pci_lookup(const struct pci_attach_args *);
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static int rtw_pci_match(device_t, cfdata_t, void *);
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static bool rtw_pci_resume(device_t, const pmf_qual_t *);
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static int rtw_pci_setup(struct rtw_pci_softc *);
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static bool rtw_pci_suspend(device_t, const pmf_qual_t *);
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CFATTACH_DECL3_NEW(rtw_pci, sizeof(struct rtw_pci_softc),
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rtw_pci_match, rtw_pci_attach, rtw_pci_detach, NULL, NULL, NULL,
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DVF_DETACH_SHUTDOWN);
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static const struct rtw_pci_product {
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u_int32_t rpp_vendor; /* PCI vendor ID */
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u_int32_t rpp_product; /* PCI product ID */
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const char *rpp_product_name;
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} rtw_pci_products[] = {
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{PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8180,
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"Realtek RTL8180 802.11 MAC/BBP"}
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, {PCI_VENDOR_BELKIN, PCI_PRODUCT_BELKIN_F5D6001, "Belkin F5D6001"}
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, {PCI_VENDOR_BELKIN, PCI_PRODUCT_BELKIN_F5D6020V3,
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"Belkin F5D6020v3 802.11b (RTL8180 MAC/BBP)"}
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, {PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DWL610,
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"DWL-610 D-Link Air 802.11b (RTL8180 MAC/BBP)"}
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, {0, 0, NULL}
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};
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static const struct rtw_pci_product *
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rtw_pci_lookup(const struct pci_attach_args *pa)
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{
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const struct rtw_pci_product *rpp;
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for (rpp = rtw_pci_products; rpp->rpp_product_name != NULL; rpp++) {
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if (PCI_VENDOR(pa->pa_id) == rpp->rpp_vendor &&
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PCI_PRODUCT(pa->pa_id) == rpp->rpp_product)
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return rpp;
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}
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return NULL;
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}
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static int
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rtw_pci_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (rtw_pci_lookup(pa) != NULL)
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return 1;
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return 0;
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}
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static void
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rtw_pci_attach(device_t parent, device_t self, void *aux)
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{
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struct rtw_pci_softc *psc = device_private(self);
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struct rtw_softc *sc = &psc->psc_rtw;
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struct rtw_regs *regs = &sc->sc_regs;
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struct pci_attach_args *pa = aux;
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const char *intrstr = NULL;
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const struct rtw_pci_product *rpp;
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sc->sc_dev = self;
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sc->sc_dmat = pa->pa_dmat;
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psc->psc_pc = pa->pa_pc;
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psc->psc_tag = pa->pa_tag;
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rpp = rtw_pci_lookup(pa);
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if (rpp == NULL) {
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printf("\n");
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panic("rtw_pci_attach: impossible");
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}
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/*
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* Get revision info, and set some chip-specific variables.
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*/
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sc->sc_rev = PCI_REVISION(pa->pa_class);
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aprint_normal(": %s, revision %d.%d signature %08x\n",
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rpp->rpp_product_name,
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(sc->sc_rev >> 4) & 0xf, sc->sc_rev & 0xf,
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pci_conf_read(psc->psc_pc, psc->psc_tag, 0x80));
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/*
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* Map the device.
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*/
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psc->psc_csr = PCI_COMMAND_MASTER_ENABLE |
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PCI_COMMAND_PARITY_ENABLE |
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PCI_COMMAND_SERR_ENABLE;
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if (pci_mapreg_map(pa, RTW_PCI_MMBA, PCI_MAPREG_TYPE_MEM, 0,
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®s->r_bt, ®s->r_bh, NULL, ®s->r_sz) == 0) {
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RTW_DPRINTF(RTW_DEBUG_ATTACH,
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("%s: %s mapped %" PRIuMAX " bytes mem space\n",
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device_xname(self), __func__, (uintmax_t)regs->r_sz));
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psc->psc_csr |= PCI_COMMAND_MEM_ENABLE;
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} else if (pci_mapreg_map(pa, RTW_PCI_IOBA, PCI_MAPREG_TYPE_IO, 0,
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®s->r_bt, ®s->r_bh, NULL, ®s->r_sz) == 0) {
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RTW_DPRINTF(RTW_DEBUG_ATTACH,
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("%s: %s mapped %" PRIuMAX " bytes I/O space\n",
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device_xname(self), __func__, (uintmax_t)regs->r_sz));
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psc->psc_csr |= PCI_COMMAND_IO_ENABLE;
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} else {
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aprint_error_dev(self, "unable to map device registers\n");
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return;
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}
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/*
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* Bring the chip out of powersave mode and initialize the
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* configuration registers.
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*/
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if (rtw_pci_setup(psc) != 0)
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return;
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/*
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* Map and establish our interrupt.
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*/
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if (pci_intr_map(pa, &psc->psc_pih)) {
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aprint_error_dev(self, "unable to map interrupt\n");
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return;
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}
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intrstr = pci_intr_string(psc->psc_pc, psc->psc_pih);
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psc->psc_ih = pci_intr_establish(psc->psc_pc, psc->psc_pih, IPL_NET,
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rtw_intr, sc);
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if (psc->psc_ih == NULL) {
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aprint_error_dev(self, "unable to establish interrupt");
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if (intrstr != NULL)
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aprint_error(" at %s", intrstr);
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aprint_error("\n");
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return;
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}
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aprint_normal_dev(self, "interrupting at %s\n", intrstr);
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/*
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* Finish off the attach.
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*/
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rtw_attach(sc);
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if (pmf_device_register(self, rtw_pci_suspend, rtw_pci_resume)) {
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pmf_class_network_register(self, &sc->sc_if);
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/*
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* Power down the socket.
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*/
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pmf_device_suspend(self, &sc->sc_qual);
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} else
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aprint_error_dev(self, "couldn't establish power handler\n");
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}
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static int
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rtw_pci_detach(device_t self, int flags)
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{
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struct rtw_pci_softc *psc = device_private(self);
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struct rtw_softc *sc = &psc->psc_rtw;
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struct rtw_regs *regs = &sc->sc_regs;
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int rc;
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if ((rc = rtw_detach(sc)) != 0)
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return rc;
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if (psc->psc_ih != NULL)
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pci_intr_disestablish(psc->psc_pc, psc->psc_ih);
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bus_space_unmap(regs->r_bt, regs->r_bh, regs->r_sz);
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return 0;
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}
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static bool
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rtw_pci_resume(device_t self, const pmf_qual_t *qual)
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{
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struct rtw_pci_softc *psc = device_private(self);
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struct rtw_softc *sc = &psc->psc_rtw;
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/* Establish the interrupt. */
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psc->psc_ih = pci_intr_establish(psc->psc_pc, psc->psc_pih, IPL_NET,
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rtw_intr, sc);
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if (psc->psc_ih == NULL) {
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aprint_error_dev(sc->sc_dev, "unable to establish interrupt\n");
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return false;
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}
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return rtw_resume(self, qual);
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}
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static bool
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rtw_pci_suspend(device_t self, const pmf_qual_t *qual)
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{
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struct rtw_pci_softc *psc = device_private(self);
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if (!rtw_suspend(self, qual))
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return false;
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/* Unhook the interrupt handler. */
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pci_intr_disestablish(psc->psc_pc, psc->psc_ih);
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psc->psc_ih = NULL;
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return true;
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}
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static int
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rtw_pci_setup(struct rtw_pci_softc *psc)
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{
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pcitag_t tag = psc->psc_tag;
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pcireg_t bhlc, csr, lattimer;
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device_t self = psc->psc_rtw.sc_dev;
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int rc;
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/* power up chip */
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rc = pci_activate(psc->psc_pc, psc->psc_tag, self, NULL);
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if (rc != 0 && rc != EOPNOTSUPP) {
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aprint_error_dev(self, "cannot activate (%d)\n", rc);
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return rc;
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}
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/* I believe the datasheet tries to warn us that the RTL8180
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* wants for 16 (0x10) to divide the latency timer.
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*/
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bhlc = pci_conf_read(psc->psc_pc, tag, PCI_BHLC_REG);
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lattimer = rounddown(PCI_LATTIMER(bhlc), 0x10);
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if (PCI_LATTIMER(bhlc) != lattimer) {
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bhlc &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
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bhlc |= (lattimer << PCI_LATTIMER_SHIFT);
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pci_conf_write(psc->psc_pc, tag, PCI_BHLC_REG, bhlc);
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}
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/* Enable the appropriate bits in the PCI CSR. */
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csr = pci_conf_read(psc->psc_pc, tag, PCI_COMMAND_STATUS_REG);
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csr &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
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csr |= psc->psc_csr;
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pci_conf_write(psc->psc_pc, tag, PCI_COMMAND_STATUS_REG, csr);
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return 0;
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}
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