316 lines
9.6 KiB
C
316 lines
9.6 KiB
C
/* $NetBSD: rccide.c,v 1.19 2009/03/14 15:36:19 dsl Exp $ */
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/*
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* Copyright (c) 2003 By Noon Software, Inc. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the authors may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: rccide.c,v 1.19 2009/03/14 15:36:19 dsl Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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static void serverworks_chip_map(struct pciide_softc *,
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struct pci_attach_args *);
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static void serverworks_setup_channel(struct ata_channel *);
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static int serverworks_pci_intr(void *);
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static int serverworkscsb6_pci_intr(void *);
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static int rccide_match(device_t, cfdata_t, void *);
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static void rccide_attach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(rccide, sizeof(struct pciide_softc),
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rccide_match, rccide_attach, NULL, NULL);
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static const struct pciide_product_desc pciide_serverworks_products[] = {
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{ PCI_PRODUCT_SERVERWORKS_OSB4_IDE,
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0,
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"ServerWorks OSB4 IDE Controller",
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serverworks_chip_map,
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},
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{ PCI_PRODUCT_SERVERWORKS_CSB5_IDE,
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0,
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"ServerWorks CSB5 IDE Controller",
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serverworks_chip_map,
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},
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{ PCI_PRODUCT_SERVERWORKS_CSB6_IDE,
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0,
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"ServerWorks CSB6 RAID/IDE Controller",
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serverworks_chip_map,
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},
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{ PCI_PRODUCT_SERVERWORKS_CSB6_RAID,
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0,
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"ServerWorks CSB6 RAID/IDE Controller",
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serverworks_chip_map,
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},
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{ PCI_PRODUCT_SERVERWORKS_HT1000_IDE,
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0,
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"ServerWorks HT-1000 IDE Controller",
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serverworks_chip_map,
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},
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{ 0,
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0,
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NULL,
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NULL,
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}
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};
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static int
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rccide_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS &&
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PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
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if (pciide_lookup_product(pa->pa_id,
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pciide_serverworks_products))
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return (2);
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}
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return (0);
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}
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static void
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rccide_attach(device_t parent, device_t self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = device_private(self);
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sc->sc_wdcdev.sc_atac.atac_dev = self;
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pciide_common_attach(sc, pa,
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pciide_lookup_product(pa->pa_id, pciide_serverworks_products));
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}
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static void
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serverworks_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *cp;
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pcireg_t interface = PCI_INTERFACE(pa->pa_class);
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pcitag_t pcib_tag;
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int channel;
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bus_size_t cmdsize, ctlsize;
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if (pciide_chipen(sc, pa) == 0)
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return;
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aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
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"bus-master DMA support present");
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pciide_mapreg_dma(sc, pa);
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aprint_verbose("\n");
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sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
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sc->sc_wdcdev.irqack = pciide_irqack;
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}
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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switch (sc->sc_pp->ide_product) {
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case PCI_PRODUCT_SERVERWORKS_OSB4_IDE:
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
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break;
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case PCI_PRODUCT_SERVERWORKS_CSB5_IDE:
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if (PCI_REVISION(pa->pa_class) < 0x92)
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
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else
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
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break;
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case PCI_PRODUCT_SERVERWORKS_CSB6_IDE:
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case PCI_PRODUCT_SERVERWORKS_CSB6_RAID:
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case PCI_PRODUCT_SERVERWORKS_HT1000_IDE:
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
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break;
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}
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sc->sc_wdcdev.sc_atac.atac_set_modes = serverworks_setup_channel;
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.sc_atac.atac_nchannels = 2;
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wdc_allocate_regs(&sc->sc_wdcdev);
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for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
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channel++) {
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cp = &sc->pciide_channels[channel];
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if (pciide_chansetup(sc, channel, interface) == 0)
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continue;
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switch (sc->sc_pp->ide_product) {
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case PCI_PRODUCT_SERVERWORKS_CSB6_IDE:
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case PCI_PRODUCT_SERVERWORKS_CSB6_RAID:
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pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
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serverworkscsb6_pci_intr);
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break;
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default:
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pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
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serverworks_pci_intr);
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}
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}
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pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0);
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pci_conf_write(pa->pa_pc, pcib_tag, 0x64,
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(pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000);
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}
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static void
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serverworks_setup_channel(struct ata_channel *chp)
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{
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struct ata_drive_datas *drvp;
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struct atac_softc *atac = chp->ch_atac;
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struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
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struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
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int channel = chp->ch_channel;
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int drive, unit, s;
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u_int32_t pio_time, dma_time, pio_mode, udma_mode;
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u_int32_t idedma_ctl;
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static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20};
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static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20};
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/* setup DMA if needed */
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pciide_channel_dma_setup(cp);
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pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40);
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dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44);
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pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48);
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udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54);
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pio_time &= ~(0xffff << (16 * channel));
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dma_time &= ~(0xffff << (16 * channel));
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pio_mode &= ~(0xff << (8 * channel + 16));
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udma_mode &= ~(0xff << (8 * channel + 16));
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udma_mode &= ~(3 << (2 * channel));
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idedma_ctl = 0;
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/* Per drive settings */
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for (drive = 0; drive < 2; drive++) {
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drvp = &chp->ch_drive[drive];
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/* If no drive, skip */
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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unit = drive + 2 * channel;
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/* add timing values, setup DMA if needed */
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pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1));
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pio_mode |= drvp->PIO_mode << (4 * unit + 16);
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if ((atac->atac_cap & ATAC_CAP_UDMA) &&
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(drvp->drive_flags & DRIVE_UDMA)) {
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/* use Ultra/DMA, check for 80-pin cable */
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if (drvp->UDMA_mode > 2 &&
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(PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag,
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PCI_SUBSYS_ID_REG))
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& (1 << (14 + channel))) == 0)
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drvp->UDMA_mode = 2;
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dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1));
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udma_mode |= drvp->UDMA_mode << (4 * unit + 16);
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udma_mode |= 1 << unit;
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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} else if ((atac->atac_cap & ATAC_CAP_DMA) &&
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(drvp->drive_flags & DRIVE_DMA)) {
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/* use Multiword DMA */
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s = splbio();
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drvp->drive_flags &= ~DRIVE_UDMA;
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splx(s);
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dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1));
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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} else {
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/* PIO only */
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s = splbio();
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drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA);
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splx(s);
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}
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}
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pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time);
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pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time);
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if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE)
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pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode);
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pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode);
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if (idedma_ctl != 0) {
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/* Add software bits in status register */
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bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
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idedma_ctl);
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}
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}
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static int
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serverworks_pci_intr(void *arg)
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{
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struct pciide_softc *sc = arg;
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struct pciide_channel *cp;
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struct ata_channel *wdc_cp;
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int rv = 0;
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int dmastat, i, crv;
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for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
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cp = &sc->pciide_channels[i];
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dmastat = bus_space_read_1(sc->sc_dma_iot,
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cp->dma_iohs[IDEDMA_CTL], 0);
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if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) !=
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IDEDMA_CTL_INTR)
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continue;
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wdc_cp = &cp->ata_channel;
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crv = wdcintr(wdc_cp);
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if (crv == 0) {
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aprint_error("%s:%d: bogus intr\n",
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device_xname(sc->sc_wdcdev.sc_atac.atac_dev), i);
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bus_space_write_1(sc->sc_dma_iot,
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cp->dma_iohs[IDEDMA_CTL], 0, dmastat);
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} else
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rv = 1;
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}
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return rv;
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}
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static int
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serverworkscsb6_pci_intr(void *arg)
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{
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struct pciide_softc *sc = arg;
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struct pciide_channel *cp;
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struct ata_channel *wdc_cp;
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int rv = 0;
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int i, crv;
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for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
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cp = &sc->pciide_channels[i];
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wdc_cp = &cp->ata_channel;
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/*
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* The CSB6 doesn't assert IDEDMA_CTL_INTR for non-DMA commands.
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* Until we find a way to know if the controller posted an
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* interrupt, always call wdcintr(), which will try to guess
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* if the interrupt was for us or not (and checks
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* IDEDMA_CTL_INTR for DMA commands only).
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*/
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crv = wdcintr(wdc_cp);
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if (crv != 0)
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rv = 1;
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}
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return rv;
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}
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