102 lines
4.2 KiB
C
102 lines
4.2 KiB
C
/* $NetBSD: ka670.h,v 1.2 2000/07/06 17:42:49 ragge Exp $ */
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/*
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* Copyright (c) 1999 Ludd, University of Lule}, Sweden.
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* All rights reserved.
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*
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* This code is derived from software contributed to Ludd by Bertram Barth.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed at Ludd, University of
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* Lule}, Sweden and its contributors.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Definitions for I/O addresses of
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*
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* VAX 4000/300 (KA670)
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*/
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#define KA670_SIDEX 0x20040004 /* SID extension register */
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#define KA670_IORESET 0x20020000 /* I/O Reset register */
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#define KA670_ROM_BASE 0x20040000 /* System module ROM */
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#define KA670_ROM_END 0x2007FFFF
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#define KA670_ROM_SIZE 0x40000
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/*
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* The following values refer to bits/bitfields within the 4 internal
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* registers controlling primary cache:
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* PR_PCTAG(124, tag-register) PR_PCIDX(125, index-register)
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* PR_PCERR(126, error-register) PR_PCSTS(127, status-register)
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*/
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#define KA670_PCTAG_TAG 0x1FFFF800 /* bits 11-29 */
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#define KA670_PCTAG_PARITY 0x40000000
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#define KA670_PCTAG_VALID 0x80000000
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#define KA670_PCIDX_INDEX 0x000007F8 /* 0x100 Q-word entries */
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#define KA670_PCERR_ADDR 0x3FFFFFFF
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#define KA670_PCS_FORCEHIT 0x00000001 /* Force hit */
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#define KA670_PCS_ENABLE 0x00000002 /* Enable primary cache */
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#define KA670_PCS_FLUSH 0x00000004 /* Flush cache */
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#define KA670_PCS_REFRESH 0x00000008 /* Enable refresh */
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#define KA670_PCS_HIT 0x00000010 /* Cache hit */
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#define KA670_PCS_INTERRUPT 0x00000020 /* Interrupt pending */
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#define KA670_PCS_TRAP2 0x00000040 /* Trap while trap */
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#define KA670_PCS_TRAP1 0x00000080 /* Micro trap/machine check */
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#define KA670_PCS_TPERR 0x00000100 /* Tag parity error */
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#define KA670_PCS_DPERR 0x00000200 /* Dal data parity error */
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#define KA670_PCS_PPERR 0x00000400 /* P data parity error */
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#define KA670_PCS_BUSERR 0x00000800 /* Bus error */
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#define KA670_PCS_BCHIT 0x00001000 /* B cache hit */
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#define KA670_PCSTS_BITS \
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"\020\015BCHIT\014BUSERR\013PPERR\012DPERR\011TPERR\010TRAP1" \
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"\007TRAP2\006INTR\005HIT\004REFRESH\003FLUSH\002ENABLE\001FORCEHIT"
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#define KA670_BCSTS_BITS \
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"\020\015BCHIT\014BUSERR\013PPERR\012DPERR\011TPERR\010TRAP1" \
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"\007TRAP2\006INTR\005HIT\004REFRESH\003FLUSH\002ENABLE\001FORCEHIT"
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/*
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* Bits in PR_ACCS (Floating Point Accelerator Register)
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*/
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#define KA670_ACCS_VECTOR (1<<0) /* Vector Unit Present */
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#define KA670_ACCS_FCHIP (1<<1) /* FPU chip present */
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#define KA670_ACCS_WEP (1<<31) /* Write Even Parity */
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/*
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* CPU-specific definitions for VAX 6000/400 (Calypso/XRP).
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*/
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/* Rigel SSC definitions */
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#define RSSC_ADDR 0x20140000 /* Phys address */
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#define RSSC_CONFIG 0x10 /* Offset */
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#define RSSC_BUSCTRL 0x20 /* Offset */
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#define RSSC_OPORT 0x30 /* Offset */
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#define RSSC_IPORT 0x40 /* Offset */
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