605 lines
15 KiB
C
605 lines
15 KiB
C
/* $NetBSD: dma.c,v 1.47 1997/10/16 10:49:00 mycroft Exp $ */
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/*
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* Copyright (c) 1994 Paul Kranenburg. All rights reserved.
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* Copyright (c) 1994 Peter Galbavy. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/errno.h>
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#include <sys/ioctl.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/buf.h>
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#include <sys/proc.h>
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#include <sys/user.h>
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#include <vm/vm.h>
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#include <machine/autoconf.h>
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#include <machine/cpu.h>
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#include <sparc/sparc/cpuvar.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/ic/ncr53c9xreg.h>
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#include <dev/ic/ncr53c9xvar.h>
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#include <sparc/dev/sbusvar.h>
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#include <sparc/dev/dmareg.h>
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#include <sparc/dev/dmavar.h>
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#include <sparc/dev/espvar.h>
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int dmaprint __P((void *, const char *));
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void dmaattach __P((struct device *, struct device *, void *));
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int dmamatch __P((struct device *, struct cfdata *, void *));
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void dma_reset __P((struct dma_softc *, int));
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void espdma_reset __P((struct dma_softc *));
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void ledma_reset __P((struct dma_softc *));
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void dma_enintr __P((struct dma_softc *));
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int dma_isintr __P((struct dma_softc *));
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int espdmaintr __P((struct dma_softc *));
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int ledmaintr __P((struct dma_softc *));
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int dma_setup __P((struct dma_softc *, caddr_t *, size_t *,
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int, size_t *));
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void dma_go __P((struct dma_softc *));
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struct cfattach dma_ca = {
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sizeof(struct dma_softc), dmamatch, dmaattach
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};
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struct cfdriver dma_cd = {
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NULL, "dma", DV_DULL
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};
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struct cfattach ledma_ca = {
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sizeof(struct dma_softc), matchbyname, dmaattach
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};
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struct cfdriver ledma_cd = {
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NULL, "ledma", DV_DULL
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};
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int
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dmaprint(aux, name)
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void *aux;
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const char *name;
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{
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register struct confargs *ca = aux;
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if (name)
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printf("[%s at %s]", ca->ca_ra.ra_name, name);
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printf(" slot 0x%x offset 0x%x", ca->ca_slot, ca->ca_offset);
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return (UNCONF);
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}
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int
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dmamatch(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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register struct confargs *ca = aux;
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register struct romaux *ra = &ca->ca_ra;
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if (strcmp(cf->cf_driver->cd_name, ra->ra_name) &&
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strcmp("espdma", ra->ra_name))
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return (0);
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if (ca->ca_bustype == BUS_SBUS)
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return (1);
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ra->ra_len = NBPG;
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return (probeget(ra->ra_vaddr, 4) != -1);
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}
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/*
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* Attach all the sub-devices we can find
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*/
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void
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dmaattach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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register struct confargs *ca = aux;
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struct dma_softc *sc = (void *)self;
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#if defined(SUN4C) || defined(SUN4M)
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int node;
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struct confargs oca;
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char *name;
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#endif
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if (ca->ca_ra.ra_vaddr == NULL || ca->ca_ra.ra_nvaddrs == 0)
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ca->ca_ra.ra_vaddr =
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mapiodev(ca->ca_ra.ra_reg, 0, ca->ca_ra.ra_len);
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sc->sc_regs = (struct dma_regs *) ca->ca_ra.ra_vaddr;
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/*
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* If we're a ledma, check to see what cable type is currently
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* active and set the appropriate bit in the ledma csr so that
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* it gets used. If we didn't netboot, the PROM won't have the
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* "cable-selection" property; default to TP and then the user
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* can change it via a "link0" option to ifconfig.
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*/
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if (strcmp(ca->ca_ra.ra_name, "ledma") == 0) {
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char *cabletype = getpropstring(ca->ca_ra.ra_node,
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"cable-selection");
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if (strcmp(cabletype, "tpe") == 0) {
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sc->sc_regs->csr |= DE_AUI_TP;
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} else if (strcmp(cabletype, "aui") == 0) {
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sc->sc_regs->csr &= ~DE_AUI_TP;
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} else {
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/* assume TP if nothing there */
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sc->sc_regs->csr |= DE_AUI_TP;
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}
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delay(20000); /* manual says we need 20ms delay */
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}
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/*
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* Get transfer burst size from PROM and plug it into the
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* controller registers. This is needed on the Sun4m; do
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* others need it too?
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*/
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if (CPU_ISSUN4M) {
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int sbusburst = ((struct sbus_softc *)parent)->sc_burst;
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if (sbusburst == 0)
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sbusburst = SBUS_BURST_32 - 1; /* 1->16 */
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sc->sc_burst = getpropint(ca->ca_ra.ra_node,"burst-sizes", -1);
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if (sc->sc_burst == -1)
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/* take SBus burst sizes */
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sc->sc_burst = sbusburst;
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/* Clamp at parent's burst sizes */
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sc->sc_burst &= sbusburst;
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}
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printf(": rev ");
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sc->sc_rev = sc->sc_regs->csr & D_DEV_ID;
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switch (sc->sc_rev) {
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case DMAREV_0:
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printf("0");
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break;
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case DMAREV_ESC:
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printf("esc");
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break;
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case DMAREV_1:
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printf("1");
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break;
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case DMAREV_PLUS:
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printf("1+");
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break;
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case DMAREV_2:
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printf("2");
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break;
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default:
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printf("unknown (0x%x)", sc->sc_rev);
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}
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printf("\n");
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/* indirect functions */
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if (sc->sc_dev.dv_cfdata->cf_attach == &dma_ca) {
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sc->reset = espdma_reset;
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sc->intr = espdmaintr;
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} else {
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sc->reset = ledma_reset;
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sc->intr = ledmaintr;
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}
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sc->enintr = dma_enintr;
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sc->isintr = dma_isintr;
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sc->setup = dma_setup;
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sc->go = dma_go;
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sc->sc_node = ca->ca_ra.ra_node;
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if (CPU_ISSUN4)
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goto espsearch;
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#if defined(SUN4C) || defined(SUN4M)
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if (ca->ca_bustype == BUS_SBUS)
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sbus_establish(&sc->sc_sd, &sc->sc_dev);
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/* Propagate bootpath */
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if (ca->ca_ra.ra_bp != NULL &&
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(strcmp(ca->ca_ra.ra_bp->name, "espdma") == 0 ||
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strcmp(ca->ca_ra.ra_bp->name, "dma") == 0 ||
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strcmp(ca->ca_ra.ra_bp->name, "ledma") == 0))
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oca.ca_ra.ra_bp = ca->ca_ra.ra_bp + 1;
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else
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oca.ca_ra.ra_bp = NULL;
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/* search through children */
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node = firstchild(sc->sc_node);
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if (node != 0) do {
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name = getpropstring(node, "name");
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if (!romprop(&oca.ca_ra, name, node))
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continue;
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sbus_translate(parent, &oca);
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oca.ca_bustype = BUS_SBUS;
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(void) config_found(&sc->sc_dev, (void *)&oca, dmaprint);
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} while ((node = nextsibling(node)) != 0); else
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#endif /* SUN4C || SUN4M */
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if (strcmp(ca->ca_ra.ra_name, "dma") == 0) {
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espsearch:
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/*
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* find the ESP by poking around the esp device structures
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*
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* What happens here is that if the esp driver has not been
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* configured, then this returns a NULL pointer. Then when the
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* esp actually gets configured, it does the opposing test, and
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* if the sc->sc_dma field in it's softc is NULL, then tries to
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* find the matching dma driver.
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*
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*/
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sc->sc_esp = (struct esp_softc *)
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getdevunit("esp", sc->sc_dev.dv_unit);
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/*
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* and a back pointer to us, for DMA
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*/
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if (sc->sc_esp)
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sc->sc_esp->sc_dma = sc;
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}
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}
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#define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \
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int count = 500000; \
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while ((COND) && --count > 0) DELAY(1); \
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if (count == 0) { \
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printf("%s: line %d: CSR = 0x%lx\n", __FILE__, __LINE__, \
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(SC)->sc_regs->csr); \
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if (DONTPANIC) \
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printf(MSG); \
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else \
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panic(MSG); \
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} \
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} while (0)
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#define DMA_DRAIN(sc, dontpanic) do { \
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/* \
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* DMA rev0 & rev1: we are not allowed to touch the DMA "flush" \
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* and "drain" bits while it is still thinking about a \
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* request. \
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* other revs: D_R_PEND bit reads as 0 \
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*/ \
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DMAWAIT(sc, sc->sc_regs->csr & D_R_PEND, "R_PEND", dontpanic); \
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/* \
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* Select drain bit based on revision \
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* also clears errors and D_TC flag \
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*/ \
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if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \
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DMACSR(sc) |= D_DRAIN; \
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else \
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DMACSR(sc) |= D_INVALIDATE; \
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/* \
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* Wait for draining to finish \
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* rev0 & rev1 call this PACKCNT \
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*/ \
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DMAWAIT(sc, sc->sc_regs->csr & D_DRAINING, "DRAINING", dontpanic);\
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} while(0)
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void
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dma_reset(sc, isledma)
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struct dma_softc *sc;
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int isledma;
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{
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DMA_DRAIN(sc, 1);
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DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */
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DMACSR(sc) |= D_RESET; /* reset DMA */
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DELAY(200); /* what should this be ? */
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/*DMAWAIT1(sc); why was this here? */
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DMACSR(sc) &= ~D_RESET; /* de-assert reset line */
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DMACSR(sc) |= D_INT_EN; /* enable interrupts */
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if (sc->sc_rev > DMAREV_1 && isledma == 0)
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DMACSR(sc) |= D_FASTER;
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switch (sc->sc_rev) {
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case DMAREV_2:
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sc->sc_regs->csr &= ~D_BURST_SIZE; /* must clear first */
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if (sc->sc_burst & SBUS_BURST_32) {
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DMACSR(sc) |= D_BURST_32;
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} else if (sc->sc_burst & SBUS_BURST_16) {
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DMACSR(sc) |= D_BURST_16;
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} else {
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DMACSR(sc) |= D_BURST_0;
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}
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break;
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case DMAREV_ESC:
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DMACSR(sc) |= D_AUTODRAIN; /* Auto-drain */
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if (sc->sc_burst & SBUS_BURST_32) {
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DMACSR(sc) &= ~0x800;
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} else
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DMACSR(sc) |= 0x800;
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break;
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default:
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}
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sc->sc_active = 0; /* and of course we aren't */
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}
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void
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espdma_reset(sc)
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struct dma_softc *sc;
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{
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dma_reset(sc, 0);
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}
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void
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ledma_reset(sc)
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struct dma_softc *sc;
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{
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dma_reset(sc, 1);
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}
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void
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dma_enintr(sc)
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struct dma_softc *sc;
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{
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sc->sc_regs->csr |= D_INT_EN;
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}
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int
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dma_isintr(sc)
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struct dma_softc *sc;
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{
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return (sc->sc_regs->csr & (D_INT_PEND|D_ERR_PEND));
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}
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#define DMAMAX(a) (0x01000000 - ((a) & 0x00ffffff))
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/*
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* setup a dma transfer
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*/
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int
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dma_setup(sc, addr, len, datain, dmasize)
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struct dma_softc *sc;
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caddr_t *addr;
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size_t *len;
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int datain;
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size_t *dmasize; /* IN-OUT */
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{
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u_long csr;
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DMA_DRAIN(sc, 0);
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#if 0
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DMACSR(sc) &= ~D_INT_EN;
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#endif
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sc->sc_dmaaddr = addr;
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sc->sc_dmalen = len;
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NCR_DMA(("%s: start %d@%p,%d\n", sc->sc_dev.dv_xname,
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*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
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/*
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* the rules say we cannot transfer more than the limit
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* of this DMA chip (64k for old and 16Mb for new),
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* and we cannot cross a 16Mb boundary.
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*/
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*dmasize = sc->sc_dmasize =
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min(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
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NCR_DMA(("dma_setup: dmasize = %d\n", sc->sc_dmasize));
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/* Program the DMA address */
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if (CPU_ISSUN4M && sc->sc_dmasize) {
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/*
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* Use dvma mapin routines to map the buffer into DVMA space.
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*/
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sc->sc_dvmaaddr = *sc->sc_dmaaddr;
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sc->sc_dvmakaddr = kdvma_mapin(sc->sc_dvmaaddr,
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sc->sc_dmasize, 0);
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if (sc->sc_dvmakaddr == NULL)
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panic("dma: cannot allocate DVMA address");
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DMADDR(sc) = sc->sc_dvmakaddr;
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} else
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DMADDR(sc) = *sc->sc_dmaaddr;
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if (sc->sc_rev == DMAREV_ESC) {
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/* DMA ESC chip bug work-around */
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register long bcnt = sc->sc_dmasize;
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register long eaddr = bcnt + (long)*sc->sc_dmaaddr;
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if ((eaddr & PGOFSET) != 0)
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bcnt = roundup(bcnt, NBPG);
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DMACNT(sc) = bcnt;
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}
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/* Setup DMA control register */
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csr = DMACSR(sc);
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if (datain)
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csr |= D_WRITE;
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else
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csr &= ~D_WRITE;
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csr |= D_INT_EN;
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DMACSR(sc) = csr;
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return 0;
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}
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void
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dma_go(sc)
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struct dma_softc *sc;
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{
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/* Start DMA */
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DMACSR(sc) |= D_EN_DMA;
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sc->sc_active = 1;
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}
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/*
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* Pseudo (chained) interrupt from the esp driver to kick the
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* current running DMA transfer. I am replying on espintr() to
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* pickup and clean errors for now
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*
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* return 1 if it was a DMA continue.
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*/
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int
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espdmaintr(sc)
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struct dma_softc *sc;
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{
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struct ncr53c9x_softc *nsc = &sc->sc_esp->sc_ncr53c9x;
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char bits[64];
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int trans, resid;
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u_long csr;
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csr = DMACSR(sc);
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NCR_DMA(("%s: intr: addr %p, csr %s\n", sc->sc_dev.dv_xname,
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DMADDR(sc), bitmask_snprintf(csr, DMACSRBITS, bits,
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sizeof(bits))));
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if (csr & D_ERR_PEND) {
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DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */
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DMACSR(sc) |= D_INVALIDATE;
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printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname,
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bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits)));
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return -1;
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}
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/* This is an "assertion" :) */
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if (sc->sc_active == 0)
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panic("dmaintr: DMA wasn't active");
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DMA_DRAIN(sc, 0);
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/* DMA has stopped */
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|
DMACSR(sc) &= ~D_EN_DMA;
|
|
sc->sc_active = 0;
|
|
|
|
if (sc->sc_dmasize == 0) {
|
|
/* A "Transfer Pad" operation completed */
|
|
NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n",
|
|
NCR_READ_REG(nsc, NCR_TCL) |
|
|
(NCR_READ_REG(nsc, NCR_TCM) << 8),
|
|
NCR_READ_REG(nsc, NCR_TCL),
|
|
NCR_READ_REG(nsc, NCR_TCM)));
|
|
return 0;
|
|
}
|
|
|
|
resid = 0;
|
|
/*
|
|
* If a transfer onto the SCSI bus gets interrupted by the device
|
|
* (e.g. for a SAVEPOINTER message), the data in the FIFO counts
|
|
* as residual since the ESP counter registers get decremented as
|
|
* bytes are clocked into the FIFO.
|
|
*/
|
|
if (!(csr & D_WRITE) &&
|
|
(resid = (NCR_READ_REG(nsc, NCR_FFLAG) & NCRFIFO_FF)) != 0) {
|
|
NCR_DMA(("dmaintr: empty esp FIFO of %d ", resid));
|
|
}
|
|
|
|
if ((nsc->sc_espstat & NCRSTAT_TC) == 0) {
|
|
/*
|
|
* `Terminal count' is off, so read the residue
|
|
* out of the ESP counter registers.
|
|
*/
|
|
resid += (NCR_READ_REG(nsc, NCR_TCL) |
|
|
(NCR_READ_REG(nsc, NCR_TCM) << 8) |
|
|
((nsc->sc_cfg2 & NCRCFG2_FE)
|
|
? (NCR_READ_REG(nsc, NCR_TCH) << 16)
|
|
: 0));
|
|
|
|
if (resid == 0 && sc->sc_dmasize == 65536 &&
|
|
(nsc->sc_cfg2 & NCRCFG2_FE) == 0)
|
|
/* A transfer of 64K is encoded as `TCL=TCM=0' */
|
|
resid = 65536;
|
|
}
|
|
|
|
trans = sc->sc_dmasize - resid;
|
|
if (trans < 0) { /* transferred < 0 ? */
|
|
#if 0
|
|
/*
|
|
* This situation can happen in perfectly normal operation
|
|
* if the ESP is reselected while using DMA to select
|
|
* another target. As such, don't print the warning.
|
|
*/
|
|
printf("%s: xfer (%d) > req (%d)\n",
|
|
sc->sc_dev.dv_xname, trans, sc->sc_dmasize);
|
|
#endif
|
|
trans = sc->sc_dmasize;
|
|
}
|
|
|
|
NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n",
|
|
NCR_READ_REG(nsc, NCR_TCL),
|
|
NCR_READ_REG(nsc, NCR_TCM),
|
|
(nsc->sc_cfg2 & NCRCFG2_FE)
|
|
? NCR_READ_REG(nsc, NCR_TCH) : 0,
|
|
trans, resid));
|
|
|
|
if (csr & D_WRITE)
|
|
cpuinfo.cache_flush(*sc->sc_dmaaddr, trans);
|
|
|
|
if (CPU_ISSUN4M && sc->sc_dvmakaddr)
|
|
dvma_mapout((vm_offset_t)sc->sc_dvmakaddr,
|
|
(vm_offset_t)sc->sc_dvmaaddr, sc->sc_dmasize);
|
|
|
|
*sc->sc_dmalen -= trans;
|
|
*sc->sc_dmaaddr += trans;
|
|
|
|
#if 0 /* this is not normal operation just yet */
|
|
if (*sc->sc_dmalen == 0 ||
|
|
nsc->sc_phase != nsc->sc_prevphase)
|
|
return 0;
|
|
|
|
/* and again */
|
|
dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
|
|
return 1;
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Pseudo (chained) interrupt from the le driver to handle DMA
|
|
* errors.
|
|
*
|
|
* XXX: untested
|
|
*/
|
|
int
|
|
ledmaintr(sc)
|
|
struct dma_softc *sc;
|
|
{
|
|
char bits[64];
|
|
u_long csr;
|
|
|
|
csr = DMACSR(sc);
|
|
|
|
if (csr & D_ERR_PEND) {
|
|
DMACSR(sc) &= ~D_EN_DMA; /* Stop DMA */
|
|
DMACSR(sc) |= D_INVALIDATE;
|
|
printf("%s: error: csr=%s\n", sc->sc_dev.dv_xname,
|
|
bitmask_snprintf(csr, DMACSRBITS, bits, sizeof(bits)));
|
|
DMA_RESET(sc);
|
|
}
|
|
return 1;
|
|
}
|