31e40c8ce1
MIPS32 4Kc CPU board, with support for the MIPS64 5Kc and the QED RM5261 CPU boards to follow. The cs4281 audio hasn't been tested, there are some interrupt problems with onboard the pciide, but all other on-board peripherals work. The evbmips port will support more MIPS evaluation boards in the future.
182 lines
5.9 KiB
C
182 lines
5.9 KiB
C
/* $NetBSD: intr.h,v 1.1 2002/03/07 14:44:00 simonb Exp $ */
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/*-
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* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _EVBMIPS_INTR_H_
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#define _EVBMIPS_INTR_H_
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#include <sys/device.h>
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#include <sys/lock.h>
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#include <sys/queue.h>
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#define IPL_NONE 0 /* disable only this interrupt */
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#define IPL_SOFT 1 /* generic software interrupts (SI 0) */
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#define IPL_SOFTCLOCK 2 /* clock software interrupts (SI 0) */
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#define IPL_SOFTNET 3 /* network software interrupts (SI 1) */
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#define IPL_SOFTSERIAL 4 /* serial software interrupts (SI 1) */
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#define IPL_BIO 5 /* disable block I/O interrupts */
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#define IPL_NET 6 /* disable network interrupts */
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#define IPL_TTY 7 /* disable terminal interrupts */
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#define IPL_SERIAL 7 /* disable serial interrupts */
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#define IPL_CLOCK 8 /* disable clock interrupts */
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#define IPL_HIGH 8 /* disable all interrupts */
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#define _IPL_NSOFT 4
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#define _IPL_N 9
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#define _IPL_SI0_FIRST IPL_SOFT
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#define _IPL_SI0_LAST IPL_SOFTCLOCK
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#define _IPL_SI1_FIRST IPL_SOFTNET
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#define _IPL_SI1_LAST IPL_SOFTSERIAL
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#define IPL_SOFTNAMES { \
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"misc", \
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"clock", \
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"net", \
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"serial", \
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}
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#define IST_UNUSABLE -1 /* interrupt cannot be used */
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#define IST_NONE 0 /* none (dummy) */
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#define IST_PULSE 1 /* pulsed */
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#define IST_EDGE 2 /* edge-triggered */
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#define IST_LEVEL 3 /* level-triggered */
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#ifdef _KERNEL
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extern const u_int32_t ipl_sr_bits[_IPL_N];
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extern const u_int32_t ipl_si_to_sr[_IPL_NSOFT];
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extern int _splraise(int);
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extern int _spllower(int);
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extern int _splset(int);
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extern int _splget(int);
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extern int _splnone(int);
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extern int _setsoftintr(int);
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extern int _clrsoftintr(int);
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#define splhigh() _splraise(ipl_sr_bits[IPL_HIGH])
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#define spl0() (void) _spllower(0)
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#define splx(s) (void) _splset(s)
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#define splbio() _splraise(ipl_sr_bits[IPL_BIO])
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#define splnet() _splraise(ipl_sr_bits[IPL_NET])
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#define spltty() _splraise(ipl_sr_bits[IPL_TTY])
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#define splserial() _splraise(ipl_sr_bits[IPL_SERIAL])
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#define splvm() spltty()
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#define splclock() _splraise(ipl_sr_bits[IPL_CLOCK])
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#define splstatclock() splclock()
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#define splsched() splclock()
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#define spllock() splhigh()
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#define spllpt() spltty()
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#define splsoft() _splraise(ipl_sr_bits[IPL_SOFT])
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#define splsoftclock() _splraise(ipl_sr_bits[IPL_SOFTCLOCK])
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#define splsoftnet() _splraise(ipl_sr_bits[IPL_SOFTNET])
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#define splsoftserial() _splraise(ipl_sr_bits[IPL_SOFTSERIAL])
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#define spllowersoftclock() _spllower(ipl_sr_bits[IPL_SOFTCLOCK])
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struct evbmips_intrhand {
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LIST_ENTRY(evbmips_intrhand) ih_q;
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int (*ih_func)(void *);
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void *ih_arg;
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int ih_irq;
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};
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#define setsoft(x) \
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do { \
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_setsoftintr(ipl_si_to_sr[(x) - IPL_SOFT]); \
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} while (0)
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struct evbmips_soft_intrhand {
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TAILQ_ENTRY(evbmips_soft_intrhand)
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sih_q;
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struct evbmips_soft_intr *sih_intrhead;
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void (*sih_fn)(void *);
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void *sih_arg;
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int sih_pending;
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};
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struct evbmips_soft_intr {
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TAILQ_HEAD(, evbmips_soft_intrhand)
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softintr_q;
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struct evcnt softintr_evcnt;
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struct simplelock softintr_slock;
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unsigned long softintr_ipl;
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};
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void *softintr_establish(int, void (*)(void *), void *);
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void softintr_disestablish(void *);
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void softintr_init(void);
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void softintr_dispatch(void);
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#define softintr_schedule(arg) \
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do { \
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struct evbmips_soft_intrhand *__sih = (arg); \
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struct evbmips_soft_intr *__si = __sih->sih_intrhead; \
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int __s; \
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\
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__s = splhigh(); \
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simple_lock(&__si->softintr_slock); \
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if (__sih->sih_pending == 0) { \
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TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \
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__sih->sih_pending = 1; \
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setsoft(__si->softintr_ipl); \
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} \
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simple_unlock(&__si->softintr_slock); \
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splx(__s); \
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} while (0)
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/* XXX For legacy software interrupts. */
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extern struct evbmips_soft_intrhand *softnet_intrhand;
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#define setsoftnet() softintr_schedule(softnet_intrhand)
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extern struct evcnt mips_int5_evcnt; /* XXX clock XXX */
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void evbmips_intr_init(void);
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void intr_init(void);
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void evbmips_iointr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
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void *evbmips_intr_establish(int, int (*)(void *), void *);
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void evbmips_intr_disestablish(void *);
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#endif /* _KERNEL */
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#endif /* ! _EVBMIPS_INTR_H_ */
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