589 lines
15 KiB
C
589 lines
15 KiB
C
/* $NetBSD: pcs_bus_mem_common.c,v 1.10 1996/10/23 04:12:32 cgd Exp $ */
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/*
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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/*
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* Common PCI Chipset "bus I/O" functions, for chipsets which have to
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* deal with only a single PCI interface chip in a machine.
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*
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* uses:
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* CHIP name of the 'chip' it's being compiled for.
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* CHIP_D_MEM_BASE Dense Mem space base to use.
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* CHIP_S_MEM_BASE Sparse Mem space base to use.
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*/
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#define __C(A,B) __CONCAT(A,B)
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#define __S(S) __STRING(S)
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/* mapping/unmapping */
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int __C(CHIP,_mem_map) __P((void *, bus_addr_t, bus_size_t, int,
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bus_space_handle_t *));
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void __C(CHIP,_mem_unmap) __P((void *, bus_space_handle_t,
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bus_size_t));
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int __C(CHIP,_mem_subregion) __P((void *, bus_space_handle_t,
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bus_size_t, bus_size_t, bus_space_handle_t *));
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/* allocation/deallocation */
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int __C(CHIP,_mem_alloc) __P((void *, bus_addr_t, bus_addr_t,
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bus_size_t, bus_size_t, bus_addr_t, int, bus_addr_t *,
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bus_space_handle_t *));
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void __C(CHIP,_mem_free) __P((void *, bus_space_handle_t,
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bus_size_t));
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/* read (single) */
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u_int8_t __C(CHIP,_mem_read_1) __P((void *, bus_space_handle_t,
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bus_size_t));
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u_int16_t __C(CHIP,_mem_read_2) __P((void *, bus_space_handle_t,
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bus_size_t));
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u_int32_t __C(CHIP,_mem_read_4) __P((void *, bus_space_handle_t,
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bus_size_t));
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u_int64_t __C(CHIP,_mem_read_8) __P((void *, bus_space_handle_t,
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bus_size_t));
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/* read multiple */
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void __C(CHIP,_mem_read_multi_1) __P((void *, bus_space_handle_t,
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bus_size_t, u_int8_t *, bus_size_t));
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void __C(CHIP,_mem_read_multi_2) __P((void *, bus_space_handle_t,
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bus_size_t, u_int16_t *, bus_size_t));
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void __C(CHIP,_mem_read_multi_4) __P((void *, bus_space_handle_t,
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bus_size_t, u_int32_t *, bus_size_t));
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void __C(CHIP,_mem_read_multi_8) __P((void *, bus_space_handle_t,
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bus_size_t, u_int64_t *, bus_size_t));
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/* read region */
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void __C(CHIP,_mem_read_region_1) __P((void *, bus_space_handle_t,
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bus_size_t, u_int8_t *, bus_size_t));
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void __C(CHIP,_mem_read_region_2) __P((void *, bus_space_handle_t,
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bus_size_t, u_int16_t *, bus_size_t));
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void __C(CHIP,_mem_read_region_4) __P((void *, bus_space_handle_t,
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bus_size_t, u_int32_t *, bus_size_t));
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void __C(CHIP,_mem_read_region_8) __P((void *, bus_space_handle_t,
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bus_size_t, u_int64_t *, bus_size_t));
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/* write (single) */
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void __C(CHIP,_mem_write_1) __P((void *, bus_space_handle_t,
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bus_size_t, u_int8_t));
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void __C(CHIP,_mem_write_2) __P((void *, bus_space_handle_t,
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bus_size_t, u_int16_t));
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void __C(CHIP,_mem_write_4) __P((void *, bus_space_handle_t,
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bus_size_t, u_int32_t));
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void __C(CHIP,_mem_write_8) __P((void *, bus_space_handle_t,
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bus_size_t, u_int64_t));
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/* write multiple */
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void __C(CHIP,_mem_write_multi_1) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int8_t *, bus_size_t));
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void __C(CHIP,_mem_write_multi_2) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int16_t *, bus_size_t));
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void __C(CHIP,_mem_write_multi_4) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int32_t *, bus_size_t));
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void __C(CHIP,_mem_write_multi_8) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int64_t *, bus_size_t));
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/* write region */
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void __C(CHIP,_mem_write_region_1) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int8_t *, bus_size_t));
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void __C(CHIP,_mem_write_region_2) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int16_t *, bus_size_t));
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void __C(CHIP,_mem_write_region_4) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int32_t *, bus_size_t));
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void __C(CHIP,_mem_write_region_8) __P((void *, bus_space_handle_t,
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bus_size_t, const u_int64_t *, bus_size_t));
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/* barrier */
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void __C(CHIP,_mem_barrier) __P((void *, bus_space_handle_t,
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bus_size_t, bus_size_t, int));
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static struct alpha_bus_space __C(CHIP,_mem_space) = {
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/* cookie */
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NULL,
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/* mapping/unmapping */
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__C(CHIP,_mem_map),
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__C(CHIP,_mem_unmap),
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__C(CHIP,_mem_subregion),
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/* allocation/deallocation */
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__C(CHIP,_mem_alloc),
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__C(CHIP,_mem_free),
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/* read (single) */
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__C(CHIP,_mem_read_1),
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__C(CHIP,_mem_read_2),
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__C(CHIP,_mem_read_4),
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__C(CHIP,_mem_read_8),
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/* read multi */
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__C(CHIP,_mem_read_multi_1),
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__C(CHIP,_mem_read_multi_2),
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__C(CHIP,_mem_read_multi_4),
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__C(CHIP,_mem_read_multi_8),
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/* read region */
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__C(CHIP,_mem_read_region_1),
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__C(CHIP,_mem_read_region_2),
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__C(CHIP,_mem_read_region_4),
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__C(CHIP,_mem_read_region_8),
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/* write (single) */
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__C(CHIP,_mem_write_1),
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__C(CHIP,_mem_write_2),
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__C(CHIP,_mem_write_4),
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__C(CHIP,_mem_write_8),
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/* write multi */
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__C(CHIP,_mem_write_multi_1),
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__C(CHIP,_mem_write_multi_2),
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__C(CHIP,_mem_write_multi_4),
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__C(CHIP,_mem_write_multi_8),
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/* write region */
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__C(CHIP,_mem_write_region_1),
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__C(CHIP,_mem_write_region_2),
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__C(CHIP,_mem_write_region_4),
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__C(CHIP,_mem_write_region_8),
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/* set multi */
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/* XXX IMPLEMENT */
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/* set region */
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/* XXX IMPLEMENT */
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/* copy */
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/* XXX IMPLEMENT */
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/* barrier */
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__C(CHIP,_mem_barrier),
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};
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bus_space_tag_t
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__C(CHIP,_bus_mem_init)(iov)
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void *iov;
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{
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bus_space_tag_t h = &__C(CHIP,_mem_space);;
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h->abs_cookie = iov;
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return (h);
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}
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int
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__C(CHIP,_mem_map)(v, memaddr, memsize, cacheable, memhp)
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void *v;
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bus_addr_t memaddr;
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bus_size_t memsize;
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int cacheable;
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bus_space_handle_t *memhp;
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{
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if (cacheable) {
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#ifdef CHIP_D_MEM_W1_START
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if (memaddr >= CHIP_D_MEM_W1_START(v) &&
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memaddr <= CHIP_D_MEM_W1_END(v)) {
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*memhp = ALPHA_PHYS_TO_K0SEG(CHIP_D_MEM_W1_BASE(v)) +
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(memaddr & CHIP_D_MEM_W1_MASK(v));
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} else
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#endif
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{
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printf("\n");
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#ifdef CHIP_D_MEM_W1_START
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printf("%s: window[1]=0x%lx-0x%lx\n",
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__S(__C(CHIP,_mem_map)), CHIP_D_MEM_W1_START(v),
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CHIP_D_MEM_W1_END(v)-1);
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#endif
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panic("%s: don't know how to map %lx cacheable",
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__S(__C(CHIP,_mem_map)), memaddr);
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}
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} else {
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#ifdef CHIP_S_MEM_W1_START
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if (memaddr >= CHIP_S_MEM_W1_START(v) &&
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memaddr <= CHIP_S_MEM_W1_END(v)) {
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*memhp = (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W1_BASE(v)) >> 5) +
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(memaddr & CHIP_S_MEM_W1_MASK(v));
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} else
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#endif
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#ifdef CHIP_S_MEM_W2_START
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if (memaddr >= CHIP_S_MEM_W2_START(v) &&
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memaddr <= CHIP_S_MEM_W2_END(v)) {
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*memhp = (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W2_BASE(v)) >> 5) +
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(memaddr & CHIP_S_MEM_W2_MASK(v));
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} else
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#endif
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#ifdef CHIP_S_MEM_W3_START
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if (memaddr >= CHIP_S_MEM_W3_START(v) &&
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memaddr <= CHIP_S_MEM_W3_END(v)) {
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*memhp = (ALPHA_PHYS_TO_K0SEG(CHIP_S_MEM_W3_BASE(v)) >> 5) +
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(memaddr & CHIP_S_MEM_W3_MASK(v));
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} else
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#endif
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{
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printf("\n");
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#ifdef CHIP_S_MEM_W1_START
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printf("%s: window[1]=0x%lx-0x%lx\n",
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__S(__C(CHIP,_mem_map)), CHIP_S_MEM_W1_START(v),
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CHIP_S_MEM_W1_END(v)-1);
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#endif
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#ifdef CHIP_S_MEM_W2_START
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printf("%s: window[2]=0x%lx-0x%lx\n",
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__S(__C(CHIP,_mem_map)), CHIP_S_MEM_W2_START(v),
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CHIP_S_MEM_W2_END(v)-1);
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#endif
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#ifdef CHIP_S_MEM_W3_START
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printf("%s: window[3]=0x%lx-0x%lx\n",
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__S(__C(CHIP,_mem_map)), CHIP_S_MEM_W3_START(v),
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CHIP_S_MEM_W3_END(v)-1);
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#endif
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panic("%s: don't know how to map %lx non-cacheable",
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__S(__C(CHIP,_mem_map)), memaddr);
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}
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}
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/* XXX XXX XXX XXX XXX XXX */
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return (0);
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}
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void
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__C(CHIP,_mem_unmap)(v, memh, memsize)
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void *v;
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bus_space_handle_t memh;
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bus_size_t memsize;
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{
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/* XXX nothing to do. */
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/* XXX XXX XXX XXX XXX XXX */
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}
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int
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__C(CHIP,_mem_subregion)(v, memh, offset, size, nmemh)
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void *v;
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bus_space_handle_t memh, *nmemh;
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bus_size_t offset, size;
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{
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*nmemh = memh + offset;
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return (0);
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}
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int
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__C(CHIP,_mem_alloc)(v, rstart, rend, size, align, boundary, cacheable,
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addrp, bshp)
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void *v;
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bus_addr_t rstart, rend, *addrp;
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bus_size_t size, align, boundary;
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int cacheable;
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bus_space_handle_t *bshp;
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{
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/* XXX XXX XXX XXX XXX XXX */
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panic("%s not implemented", __S(__C(CHIP,_mem_alloc)));
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}
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void
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__C(CHIP,_mem_free)(v, bsh, size)
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void *v;
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bus_space_handle_t bsh;
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bus_size_t size;
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{
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/* XXX XXX XXX XXX XXX XXX */
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panic("%s not implemented", __S(__C(CHIP,_mem_free)));
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}
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u_int8_t
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__C(CHIP,_mem_read_1)(v, memh, off)
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void *v;
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bus_space_handle_t memh;
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bus_size_t off;
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{
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register bus_space_handle_t tmpmemh;
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register u_int32_t *port, val;
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register u_int8_t rval;
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register int offset;
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alpha_mb();
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if ((memh >> 63) != 0)
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return (*(u_int8_t *)(memh + off));
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tmpmemh = memh + off;
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offset = tmpmemh & 3;
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port = (u_int32_t *)((tmpmemh << 5) | (0 << 3));
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val = *port;
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rval = ((val) >> (8 * offset)) & 0xff;
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return rval;
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}
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u_int16_t
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__C(CHIP,_mem_read_2)(v, memh, off)
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void *v;
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bus_space_handle_t memh;
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bus_size_t off;
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{
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register bus_space_handle_t tmpmemh;
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register u_int32_t *port, val;
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register u_int16_t rval;
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register int offset;
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alpha_mb();
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if ((memh >> 63) != 0)
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return (*(u_int16_t *)(memh + off));
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tmpmemh = memh + off;
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offset = tmpmemh & 3;
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port = (u_int32_t *)((tmpmemh << 5) | (1 << 3));
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val = *port;
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rval = ((val) >> (8 * offset)) & 0xffff;
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return rval;
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}
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u_int32_t
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__C(CHIP,_mem_read_4)(v, memh, off)
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void *v;
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bus_space_handle_t memh;
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bus_size_t off;
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{
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register bus_space_handle_t tmpmemh;
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register u_int32_t *port, val;
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register u_int32_t rval;
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register int offset;
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alpha_mb();
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if ((memh >> 63) != 0)
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return (*(u_int32_t *)(memh + off));
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tmpmemh = memh + off;
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offset = tmpmemh & 3;
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port = (u_int32_t *)((tmpmemh << 5) | (3 << 3));
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val = *port;
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#if 0
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rval = ((val) >> (8 * offset)) & 0xffffffff;
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#else
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rval = val;
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#endif
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return rval;
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}
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u_int64_t
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__C(CHIP,_mem_read_8)(v, memh, off)
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void *v;
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bus_space_handle_t memh;
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bus_size_t off;
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{
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alpha_mb();
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if ((memh >> 63) != 0)
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return (*(u_int64_t *)(memh + off));
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/* XXX XXX XXX */
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panic("%s not implemented", __S(__C(CHIP,_mem_read_8)));
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}
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#define CHIP_mem_read_multi_N(BYTES,TYPE) \
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void \
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__C(__C(CHIP,_mem_read_multi_),BYTES)(v, h, o, a, c) \
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void *v; \
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bus_space_handle_t h; \
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bus_size_t o, c; \
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TYPE *a; \
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{ \
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\
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while (c-- > 0) { \
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__C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \
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BUS_BARRIER_READ); \
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*a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \
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} \
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}
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CHIP_mem_read_multi_N(1,u_int8_t)
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CHIP_mem_read_multi_N(2,u_int16_t)
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CHIP_mem_read_multi_N(4,u_int32_t)
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CHIP_mem_read_multi_N(8,u_int64_t)
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#define CHIP_mem_read_region_N(BYTES,TYPE) \
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void \
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__C(__C(CHIP,_mem_read_region_),BYTES)(v, h, o, a, c) \
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void *v; \
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bus_space_handle_t h; \
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bus_size_t o, c; \
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TYPE *a; \
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{ \
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\
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while (c-- > 0) { \
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*a++ = __C(__C(CHIP,_mem_read_),BYTES)(v, h, o); \
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o += sizeof *a; \
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} \
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}
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CHIP_mem_read_region_N(1,u_int8_t)
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CHIP_mem_read_region_N(2,u_int16_t)
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CHIP_mem_read_region_N(4,u_int32_t)
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CHIP_mem_read_region_N(8,u_int64_t)
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void
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__C(CHIP,_mem_write_1)(v, memh, off, val)
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void *v;
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bus_space_handle_t memh;
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bus_size_t off;
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u_int8_t val;
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{
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register bus_space_handle_t tmpmemh;
|
|
register u_int32_t *port, nval;
|
|
register int offset;
|
|
|
|
if ((memh >> 63) != 0)
|
|
(*(u_int8_t *)(memh + off)) = val;
|
|
else {
|
|
tmpmemh = memh + off;
|
|
offset = tmpmemh & 3;
|
|
nval = val << (8 * offset);
|
|
port = (u_int32_t *)((tmpmemh << 5) | (0 << 3));
|
|
*port = nval;
|
|
}
|
|
alpha_mb();
|
|
}
|
|
|
|
void
|
|
__C(CHIP,_mem_write_2)(v, memh, off, val)
|
|
void *v;
|
|
bus_space_handle_t memh;
|
|
bus_size_t off;
|
|
u_int16_t val;
|
|
{
|
|
register bus_space_handle_t tmpmemh;
|
|
register u_int32_t *port, nval;
|
|
register int offset;
|
|
|
|
if ((memh >> 63) != 0)
|
|
(*(u_int16_t *)(memh + off)) = val;
|
|
else {
|
|
tmpmemh = memh + off;
|
|
offset = tmpmemh & 3;
|
|
nval = val << (8 * offset);
|
|
port = (u_int32_t *)((tmpmemh << 5) | (1 << 3));
|
|
*port = nval;
|
|
}
|
|
alpha_mb();
|
|
}
|
|
|
|
void
|
|
__C(CHIP,_mem_write_4)(v, memh, off, val)
|
|
void *v;
|
|
bus_space_handle_t memh;
|
|
bus_size_t off;
|
|
u_int32_t val;
|
|
{
|
|
register bus_space_handle_t tmpmemh;
|
|
register u_int32_t *port, nval;
|
|
register int offset;
|
|
|
|
if ((memh >> 63) != 0)
|
|
(*(u_int32_t *)(memh + off)) = val;
|
|
else {
|
|
tmpmemh = memh + off;
|
|
offset = tmpmemh & 3;
|
|
nval = val /*<< (8 * offset)*/;
|
|
port = (u_int32_t *)((tmpmemh << 5) | (3 << 3));
|
|
*port = nval;
|
|
}
|
|
alpha_mb();
|
|
}
|
|
|
|
void
|
|
__C(CHIP,_mem_write_8)(v, memh, off, val)
|
|
void *v;
|
|
bus_space_handle_t memh;
|
|
bus_size_t off;
|
|
u_int64_t val;
|
|
{
|
|
|
|
if ((memh >> 63) != 0)
|
|
(*(u_int64_t *)(memh + off)) = val;
|
|
else {
|
|
/* XXX XXX XXX */
|
|
panic("%s not implemented",
|
|
__S(__C(CHIP,_mem_write_8)));
|
|
}
|
|
alpha_mb();
|
|
}
|
|
|
|
#define CHIP_mem_write_multi_N(BYTES,TYPE) \
|
|
void \
|
|
__C(__C(CHIP,_mem_write_multi_),BYTES)(v, h, o, a, c) \
|
|
void *v; \
|
|
bus_space_handle_t h; \
|
|
bus_size_t o, c; \
|
|
const TYPE *a; \
|
|
{ \
|
|
\
|
|
while (c-- > 0) { \
|
|
__C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \
|
|
__C(CHIP,_mem_barrier)(v, h, o, sizeof *a, \
|
|
BUS_BARRIER_WRITE); \
|
|
} \
|
|
}
|
|
CHIP_mem_write_multi_N(1,u_int8_t)
|
|
CHIP_mem_write_multi_N(2,u_int16_t)
|
|
CHIP_mem_write_multi_N(4,u_int32_t)
|
|
CHIP_mem_write_multi_N(8,u_int64_t)
|
|
|
|
#define CHIP_mem_write_region_N(BYTES,TYPE) \
|
|
void \
|
|
__C(__C(CHIP,_mem_write_region_),BYTES)(v, h, o, a, c) \
|
|
void *v; \
|
|
bus_space_handle_t h; \
|
|
bus_size_t o, c; \
|
|
const TYPE *a; \
|
|
{ \
|
|
\
|
|
while (c-- > 0) { \
|
|
__C(__C(CHIP,_mem_write_),BYTES)(v, h, o, *a++); \
|
|
o += sizeof *a; \
|
|
} \
|
|
}
|
|
CHIP_mem_write_region_N(1,u_int8_t)
|
|
CHIP_mem_write_region_N(2,u_int16_t)
|
|
CHIP_mem_write_region_N(4,u_int32_t)
|
|
CHIP_mem_write_region_N(8,u_int64_t)
|
|
|
|
void
|
|
__C(CHIP,_mem_barrier)(v, h, o, l, f)
|
|
void *v;
|
|
bus_space_handle_t h;
|
|
bus_size_t o, l;
|
|
int f;
|
|
{
|
|
|
|
if ((f & BUS_BARRIER_READ) != 0)
|
|
alpha_mb();
|
|
else if ((f & BUS_BARRIER_WRITE) != 0)
|
|
alpha_wmb();
|
|
}
|