736004cf1c
This allows cats to override the BIOS (aka ABLE) settings, which enable native mode, but doesn't route the interrupts correctly. Discussed last year on tech-kern and port-cats.
377 lines
12 KiB
C
377 lines
12 KiB
C
/* $NetBSD: aceride.c,v 1.24 2008/01/01 14:57:06 chris Exp $ */
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/*
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* Copyright (c) 1999, 2000, 2001 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Manuel Bouyer.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: aceride.c,v 1.24 2008/01/01 14:57:06 chris Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/pci/pciide_acer_reg.h>
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static int acer_pcib_match(struct pci_attach_args *);
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static void acer_do_reset(struct ata_channel *, int);
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static void acer_chip_map(struct pciide_softc*, struct pci_attach_args*);
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static void acer_setup_channel(struct ata_channel*);
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static int acer_pci_intr(void *);
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static int aceride_match(struct device *, struct cfdata *, void *);
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static void aceride_attach(struct device *, struct device *, void *);
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struct aceride_softc {
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struct pciide_softc pciide_sc;
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struct pci_attach_args pcib_pa;
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};
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CFATTACH_DECL(aceride, sizeof(struct aceride_softc),
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aceride_match, aceride_attach, NULL, NULL);
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static const struct pciide_product_desc pciide_acer_products[] = {
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{ PCI_PRODUCT_ALI_M5229,
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0,
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"Acer Labs M5229 UDMA IDE Controller",
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acer_chip_map,
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},
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{ 0,
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0,
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NULL,
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NULL
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}
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};
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static int
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aceride_match(struct device *parent, struct cfdata *match,
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void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI &&
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PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
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if (pciide_lookup_product(pa->pa_id, pciide_acer_products))
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return (2);
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}
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return (0);
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}
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static void
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aceride_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = (struct pciide_softc *)self;
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pciide_common_attach(sc, pa,
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pciide_lookup_product(pa->pa_id, pciide_acer_products));
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}
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static int
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acer_pcib_match(struct pci_attach_args *pa)
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{
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/*
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* we need to access the PCI config space of the pcib, see
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* acer_do_reset()
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*/
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if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_ISA &&
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PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI &&
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M1543)
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return 1;
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return 0;
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}
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static void
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acer_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *cp;
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int channel;
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pcireg_t cr, interface;
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bus_size_t cmdsize, ctlsize;
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pcireg_t rev = PCI_REVISION(pa->pa_class);
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struct aceride_softc *acer_sc = (struct aceride_softc *)sc;
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if (pciide_chipen(sc, pa) == 0)
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return;
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aprint_verbose("%s: bus-master DMA support present",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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pciide_mapreg_dma(sc, pa);
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aprint_verbose("\n");
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sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
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if (rev >= 0x20) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA;
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if (rev >= 0xC7)
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
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else if (rev >= 0xC4)
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 5;
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else if (rev >= 0xC2)
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 4;
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else
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 2;
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}
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sc->sc_wdcdev.irqack = pciide_irqack;
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}
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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sc->sc_wdcdev.sc_atac.atac_set_modes = acer_setup_channel;
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
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pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CDRC,
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(pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CDRC) |
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ACER_CDRC_DMA_EN) & ~ACER_CDRC_FIFO_DISABLE);
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/* Enable "microsoft register bits" R/W. */
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pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR3,
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pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR3) | ACER_CCAR3_PI);
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pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR1,
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pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR1) &
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~(ACER_CHANSTATUS_RO|PCIIDE_CHAN_RO(0)|PCIIDE_CHAN_RO(1)));
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pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_CCAR2,
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pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CCAR2) &
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~ACER_CHANSTATUSREGS_RO);
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cr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG);
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cr |= (PCIIDE_CHANSTATUS_EN << PCI_INTERFACE_SHIFT);
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{
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/*
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* some BIOSes (port-cats ABLE) enable native mode, but don't
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* setup everything correctly, so allow the forcing of
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* compat mode
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*/
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bool force_compat_mode;
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bool property_is_set;
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property_is_set = prop_dictionary_get_bool(
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device_properties(&sc->sc_wdcdev.sc_atac.atac_dev),
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"ali1543-ide-force-compat-mode",
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&force_compat_mode);
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if (property_is_set && force_compat_mode) {
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cr &= ~((PCIIDE_INTERFACE_PCI(0)
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| PCIIDE_INTERFACE_PCI(1))
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<< PCI_INTERFACE_SHIFT);
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}
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}
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pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CLASS_REG, cr);
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/* Don't use cr, re-read the real register content instead */
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interface = PCI_INTERFACE(pci_conf_read(sc->sc_pc, sc->sc_tag,
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PCI_CLASS_REG));
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/* From linux: enable "Cable Detection" */
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if (rev >= 0xC2) {
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pciide_pci_write(sc->sc_pc, sc->sc_tag, ACER_0x4B,
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pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4B)
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| ACER_0x4B_CDETECT);
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}
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wdc_allocate_regs(&sc->sc_wdcdev);
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if (rev == 0xC3) {
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/* install reset bug workaround */
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if (pci_find_device(&acer_sc->pcib_pa, acer_pcib_match) == 0) {
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printf("%s: WARNING: can't find pci-isa bridge\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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} else
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sc->sc_wdcdev.reset = acer_do_reset;
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}
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for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
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channel++) {
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cp = &sc->pciide_channels[channel];
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if (pciide_chansetup(sc, channel, interface) == 0)
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continue;
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if ((interface & PCIIDE_CHAN_EN(channel)) == 0) {
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aprint_normal("%s: %s channel ignored (disabled)\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
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cp->ata_channel.ch_flags |= ATACH_DISABLED;
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continue;
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}
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/* newer controllers seems to lack the ACER_CHIDS. Sigh */
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pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
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(rev >= 0xC2) ? pciide_pci_intr : acer_pci_intr);
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}
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}
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static void
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acer_do_reset(struct ata_channel *chp, int poll)
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{
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struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
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struct aceride_softc *acer_sc = (struct aceride_softc *)sc;
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u_int8_t reg;
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/*
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* From OpenSolaris: after a reset we need to disable/enable the
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* corresponding channel, or data corruption will occur in
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* UltraDMA modes
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*/
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wdc_do_reset(chp, poll);
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reg = pciide_pci_read(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag,
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ACER_PCIB_CTRL);
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pciide_pci_write(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag,
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ACER_PCIB_CTRL, reg & ~ACER_PCIB_CTRL_ENCHAN(chp->ch_channel));
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delay(1000);
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pciide_pci_write(acer_sc->pcib_pa.pa_pc, acer_sc->pcib_pa.pa_tag,
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ACER_PCIB_CTRL, reg);
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}
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static void
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acer_setup_channel(struct ata_channel *chp)
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{
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struct ata_drive_datas *drvp;
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int drive, s;
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u_int32_t acer_fifo_udma;
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u_int32_t idedma_ctl;
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struct pciide_channel *cp = (struct pciide_channel*)chp;
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struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
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idedma_ctl = 0;
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acer_fifo_udma = pci_conf_read(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA);
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ATADEBUG_PRINT(("acer_setup_channel: old fifo/udma reg 0x%x\n",
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acer_fifo_udma), DEBUG_PROBE);
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/* setup DMA if needed */
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pciide_channel_dma_setup(cp);
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if ((chp->ch_drive[0].drive_flags | chp->ch_drive[1].drive_flags) &
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DRIVE_UDMA) { /* check 80 pins cable */
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if (pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_0x4A) &
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ACER_0x4A_80PIN(chp->ch_channel)) {
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if (chp->ch_drive[0].UDMA_mode > 2)
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chp->ch_drive[0].UDMA_mode = 2;
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if (chp->ch_drive[1].UDMA_mode > 2)
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chp->ch_drive[1].UDMA_mode = 2;
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}
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}
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for (drive = 0; drive < 2; drive++) {
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drvp = &chp->ch_drive[drive];
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/* If no drive, skip */
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if ((drvp->drive_flags & DRIVE) == 0)
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continue;
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ATADEBUG_PRINT(("acer_setup_channel: old timings reg for "
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"channel %d drive %d 0x%x\n", chp->ch_channel, drive,
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pciide_pci_read(sc->sc_pc, sc->sc_tag,
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ACER_IDETIM(chp->ch_channel, drive))), DEBUG_PROBE);
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/* clear FIFO/DMA mode */
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acer_fifo_udma &= ~(ACER_FTH_OPL(chp->ch_channel, drive, 0x3) |
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ACER_UDMA_EN(chp->ch_channel, drive) |
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ACER_UDMA_TIM(chp->ch_channel, drive, 0x7));
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/* add timing values, setup DMA if needed */
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if ((drvp->drive_flags & DRIVE_DMA) == 0 &&
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(drvp->drive_flags & DRIVE_UDMA) == 0) {
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acer_fifo_udma |=
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ACER_FTH_OPL(chp->ch_channel, drive, 0x1);
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goto pio;
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}
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acer_fifo_udma |= ACER_FTH_OPL(chp->ch_channel, drive, 0x2);
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if (drvp->drive_flags & DRIVE_UDMA) {
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/* use Ultra/DMA */
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s = splbio();
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drvp->drive_flags &= ~DRIVE_DMA;
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splx(s);
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acer_fifo_udma |= ACER_UDMA_EN(chp->ch_channel, drive);
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acer_fifo_udma |=
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ACER_UDMA_TIM(chp->ch_channel, drive,
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acer_udma[drvp->UDMA_mode]);
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/* XXX disable if one drive < UDMA3 ? */
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if (drvp->UDMA_mode >= 3) {
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pciide_pci_write(sc->sc_pc, sc->sc_tag,
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ACER_0x4B,
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pciide_pci_read(sc->sc_pc, sc->sc_tag,
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ACER_0x4B) | ACER_0x4B_UDMA66);
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}
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} else {
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/*
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* use Multiword DMA
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* Timings will be used for both PIO and DMA,
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* so adjust DMA mode if needed
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*/
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if (drvp->PIO_mode > (drvp->DMA_mode + 2))
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drvp->PIO_mode = drvp->DMA_mode + 2;
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if (drvp->DMA_mode + 2 > (drvp->PIO_mode))
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drvp->DMA_mode = (drvp->PIO_mode > 2) ?
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drvp->PIO_mode - 2 : 0;
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if (drvp->DMA_mode == 0)
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drvp->PIO_mode = 0;
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}
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idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
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pio: pciide_pci_write(sc->sc_pc, sc->sc_tag,
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ACER_IDETIM(chp->ch_channel, drive),
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acer_pio[drvp->PIO_mode]);
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}
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ATADEBUG_PRINT(("acer_setup_channel: new fifo/udma reg 0x%x\n",
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acer_fifo_udma), DEBUG_PROBE);
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pci_conf_write(sc->sc_pc, sc->sc_tag, ACER_FTH_UDMA, acer_fifo_udma);
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if (idedma_ctl != 0) {
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/* Add software bits in status register */
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bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
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idedma_ctl);
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}
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}
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static int
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acer_pci_intr(void *arg)
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{
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struct pciide_softc *sc = arg;
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struct pciide_channel *cp;
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struct ata_channel *wdc_cp;
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int i, rv, crv;
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u_int32_t chids;
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rv = 0;
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chids = pciide_pci_read(sc->sc_pc, sc->sc_tag, ACER_CHIDS);
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for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
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cp = &sc->pciide_channels[i];
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wdc_cp = &cp->ata_channel;
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/* If a compat channel skip. */
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if (cp->compat)
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continue;
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if (chids & ACER_CHIDS_INT(i)) {
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crv = wdcintr(wdc_cp);
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if (crv == 0) {
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printf("%s:%d: bogus intr\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i);
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pciide_irqack(wdc_cp);
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} else
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rv = 1;
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}
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}
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return rv;
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}
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