345 lines
9.0 KiB
C
345 lines
9.0 KiB
C
/* $NetBSD: if_re_cardbus.c,v 1.27 2011/08/01 11:20:27 drochner Exp $ */
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/*
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* Copyright (c) 2004 Jonathan Stone
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* if_re_cardbus.c:
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* Cardbus specific routines for Realtek 8169 ethernet adapter.
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* Tested for :
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* Netgear GA-511 (8169S)
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* Buffalo LPC-CB-CLGT
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_re_cardbus.c,v 1.27 2011/08/01 11:20:27 drochner Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <net/if.h>
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#include <net/if_ether.h>
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#include <net/if_media.h>
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#include <sys/bus.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/cardbus/cardbusvar.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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/*
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* Default to using PIO access for this driver. On SMP systems,
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* there appear to be problems with memory mapped mode: it looks like
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* doing too many memory mapped access back to back in rapid succession
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* can hang the bus. I'm inclined to blame this on crummy design/construction
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* on the part of Realtek. Memory mapped mode does appear to work on
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* uniprocessor systems though.
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*/
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#define RTK_USEIOSPACE
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#include <dev/ic/rtl81x9reg.h>
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#include <dev/ic/rtl81x9var.h>
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#include <dev/ic/rtl8169var.h>
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/*
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* Various supported device vendors/types and their names.
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*/
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static const struct rtk_type re_cardbus_devs[] = {
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{ PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169,
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RTK_8169, "Realtek 10/100/1000baseT" },
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{ 0, 0, 0, NULL }
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};
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static int re_cardbus_match(device_t, cfdata_t, void *);
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static void re_cardbus_attach(device_t, device_t, void *);
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static int re_cardbus_detach(device_t, int);
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struct re_cardbus_softc {
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struct rtk_softc sc_rtk; /* real rtk softc */
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/* CardBus-specific goo. */
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void *sc_ih;
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cardbus_devfunc_t sc_ct;
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pcitag_t sc_tag;
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pcireg_t sc_csr;
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int sc_bar_reg;
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pcireg_t sc_bar_val;
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};
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CFATTACH_DECL_NEW(re_cardbus, sizeof(struct re_cardbus_softc),
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re_cardbus_match, re_cardbus_attach, re_cardbus_detach, re_activate);
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const struct rtk_type *re_cardbus_lookup(const struct cardbus_attach_args *);
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void re_cardbus_setup(struct re_cardbus_softc *);
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int re_cardbus_enable(struct rtk_softc *);
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void re_cardbus_disable(struct rtk_softc *);
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const struct rtk_type *
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re_cardbus_lookup(const struct cardbus_attach_args *ca)
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{
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const struct rtk_type *t;
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for (t = re_cardbus_devs; t->rtk_name != NULL; t++) {
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if (PCI_VENDOR(ca->ca_id) == t->rtk_vid &&
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PCI_PRODUCT(ca->ca_id) == t->rtk_did) {
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return t;
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}
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}
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return NULL;
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}
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int
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re_cardbus_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct cardbus_attach_args *ca = aux;
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if (re_cardbus_lookup(ca) != NULL)
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return 1;
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return 0;
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}
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void
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re_cardbus_attach(device_t parent, device_t self, void *aux)
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{
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struct re_cardbus_softc *csc = device_private(self);
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struct rtk_softc *sc = &csc->sc_rtk;
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struct cardbus_attach_args *ca = aux;
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cardbus_devfunc_t ct = ca->ca_ct;
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const struct rtk_type *t;
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bus_addr_t adr;
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sc->sc_dev = self;
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sc->sc_dmat = ca->ca_dmat;
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csc->sc_ct = ct;
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csc->sc_tag = ca->ca_tag;
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t = re_cardbus_lookup(ca);
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if (t == NULL) {
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aprint_error("\n");
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panic("%s: impossible", __func__);
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}
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aprint_normal(": %s\n", t->rtk_name);
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/*
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* Power management hooks.
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*/
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sc->sc_enable = re_cardbus_enable;
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sc->sc_disable = re_cardbus_disable;
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/*
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* Map control/status registers.
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*/
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csc->sc_csr = PCI_COMMAND_MASTER_ENABLE;
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#ifdef RTK_USEIOSPACE
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if (Cardbus_mapreg_map(ct, RTK_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
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&sc->rtk_btag, &sc->rtk_bhandle, &adr, &sc->rtk_bsize) == 0) {
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csc->sc_csr |= PCI_COMMAND_IO_ENABLE;
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csc->sc_bar_reg = RTK_PCI_LOIO;
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csc->sc_bar_val = adr | PCI_MAPREG_TYPE_IO;
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}
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#else
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if (Cardbus_mapreg_map(ct, RTK_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
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&sc->rtk_btag, &sc->rtk_bhandle, &adr, &sc->rtk_bsize) == 0) {
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csc->sc_csr |= PCI_COMMAND_MEM_ENABLE;
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csc->sc_bar_reg = RTK_PCI_LOMEM;
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csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
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}
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#endif
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else {
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aprint_error_dev(self, "unable to map deviceregisters\n");
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return;
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}
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/*
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* Handle power management nonsense and initialize the
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* configuration registers.
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*/
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re_cardbus_setup(csc);
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sc->sc_dmat = ca->ca_dmat;
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re_attach(sc);
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/*
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* Power down the socket.
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*/
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Cardbus_function_disable(csc->sc_ct);
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}
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int
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re_cardbus_detach(device_t self, int flags)
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{
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struct re_cardbus_softc *csc = device_private(self);
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struct rtk_softc *sc = &csc->sc_rtk;
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struct cardbus_devfunc *ct = csc->sc_ct;
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int rv;
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#ifdef DIAGNOSTIC
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if (ct == NULL)
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panic("%s: cardbus softc, cardbus_devfunc NULL",
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device_xname(self));
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#endif
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rv = re_detach(sc);
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if (rv)
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return rv;
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/*
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* Unhook the interrupt handler.
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*/
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if (csc->sc_ih != NULL)
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Cardbus_intr_disestablish(ct, csc->sc_ih);
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/*
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* Release bus space and close window.
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*/
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if (csc->sc_bar_reg != 0)
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Cardbus_mapreg_unmap(ct, csc->sc_bar_reg,
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sc->rtk_btag, sc->rtk_bhandle, sc->rtk_bsize);
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return 0;
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}
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void
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re_cardbus_setup(struct re_cardbus_softc *csc)
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{
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struct rtk_softc *sc = &csc->sc_rtk;
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cardbus_devfunc_t ct = csc->sc_ct;
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cardbus_chipset_tag_t cc = ct->ct_cc;
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cardbus_function_tag_t cf = ct->ct_cf;
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pcireg_t reg, command;
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int pmreg;
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/*
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* Handle power management nonsense.
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*/
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if (cardbus_get_capability(cc, cf, csc->sc_tag,
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PCI_CAP_PWRMGMT, &pmreg, 0)) {
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command = Cardbus_conf_read(ct, csc->sc_tag,
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pmreg + PCI_PMCSR);
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if (command & PCI_PMCSR_STATE_MASK) {
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pcireg_t iobase, membase, irq;
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/* Save important PCI config data. */
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iobase = Cardbus_conf_read(ct, csc->sc_tag,
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RTK_PCI_LOIO);
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membase = Cardbus_conf_read(ct, csc->sc_tag,
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RTK_PCI_LOMEM);
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irq = Cardbus_conf_read(ct, csc->sc_tag,
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PCI_INTERRUPT_REG);
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/* Reset the power state. */
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aprint_normal_dev(sc->sc_dev,
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"chip is in D%d power mode -- setting to D0\n",
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command & PCI_PMCSR_STATE_MASK);
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command &= ~PCI_PMCSR_STATE_MASK;
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Cardbus_conf_write(ct, csc->sc_tag,
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pmreg + PCI_PMCSR, command);
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/* Restore PCI config data. */
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Cardbus_conf_write(ct, csc->sc_tag,
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RTK_PCI_LOIO, iobase);
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Cardbus_conf_write(ct, csc->sc_tag,
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RTK_PCI_LOMEM, membase);
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Cardbus_conf_write(ct, csc->sc_tag,
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PCI_INTERRUPT_REG, irq);
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}
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}
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/* Program the BAR */
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Cardbus_conf_write(ct, csc->sc_tag, csc->sc_bar_reg, csc->sc_bar_val);
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/* Enable the appropriate bits in the CARDBUS CSR. */
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reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG);
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reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
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reg |= csc->sc_csr;
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Cardbus_conf_write(ct, csc->sc_tag, PCI_COMMAND_STATUS_REG, reg);
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/*
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* Make sure the latency timer is set to some reasonable
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* value.
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*/
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reg = Cardbus_conf_read(ct, csc->sc_tag, PCI_BHLC_REG);
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if (PCI_LATTIMER(reg) < 0x40) {
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reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
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reg |= (0x40 << PCI_LATTIMER_SHIFT);
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Cardbus_conf_write(ct, csc->sc_tag, PCI_BHLC_REG, reg);
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}
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}
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int
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re_cardbus_enable(struct rtk_softc *sc)
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{
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struct re_cardbus_softc *csc = (struct re_cardbus_softc *)sc;
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cardbus_devfunc_t ct = csc->sc_ct;
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/*
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* Power on the socket.
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*/
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Cardbus_function_enable(ct);
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/*
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* Set up the PCI configuration registers.
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*/
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re_cardbus_setup(csc);
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/*
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* Map and establish the interrupt.
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*/
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csc->sc_ih = Cardbus_intr_establish(ct, IPL_NET, re_intr, sc);
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if (csc->sc_ih == NULL) {
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aprint_error_dev(sc->sc_dev,
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"unable to establish interrupt\n");
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Cardbus_function_disable(csc->sc_ct);
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return 1;
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}
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return 0;
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}
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void
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re_cardbus_disable(struct rtk_softc *sc)
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{
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struct re_cardbus_softc *csc = (struct re_cardbus_softc *)sc;
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cardbus_devfunc_t ct = csc->sc_ct;
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/* Unhook the interrupt handler. */
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Cardbus_intr_disestablish(ct, csc->sc_ih);
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csc->sc_ih = NULL;
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/* Power down the socket. */
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Cardbus_function_disable(ct);
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}
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