a8d4826eab
quirk, and use it for the 9690 as well where it's also needed. Patch by me, problem hunted down by Jiri Novotny and Zdenek Slavet and reported in PR 44002.
517 lines
15 KiB
C
517 lines
15 KiB
C
/* $NetBSD: twareg.h,v 1.11 2010/11/22 23:02:16 dholland Exp $ */
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/* $wasabi: twareg.h,v 1.14 2006/07/28 18:29:51 wrstuden Exp $ */
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/*-
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* Copyright (c) 2003-04 3ware, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD: src/sys/dev/twa/twa_reg.h,v 1.2 2004/08/18 16:14:44 vkashyap Exp $
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*/
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/*
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* 3ware driver for 9000 series storage controllers.
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*
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* Author: Vinod Kashyap
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*/
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#ifndef _PCI_TWAREG_H_
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#define _PCI_TWAREG_H_
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#if defined(_KERNEL)
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#include <sys/bus.h>
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/*
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* The following macro has no business being in twa_reg.h. It should probably
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* be defined in twa_includes.h, before the #include twa_reg.h.... But that
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* causes the API to run into build errors. Will leave it here for now...
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*/
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#define TWA_64BIT_ADDRESSES ((sizeof(bus_addr_t) == 8) ? 1 : 0)
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/*
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* Define the following here since it relies on TWA_64BIT_ADDRESSES which
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* depends on sizeof(bus_addr_t), which is not exported to userland.
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* The userland API shouldn't care about the kernel's bus_addr_t.
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* For the userland API, use the array size that we would use for 32-bit
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* addresses since that's what we use in the sg structure definition.
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* The userland API does not actually appear to use the array, but it
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* does include the array in various command structures.
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*/
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#define TWA_MAX_SG_ELEMENTS (TWA_64BIT_ADDRESSES ? 70 : 105)
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#else
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#define TWA_MAX_SG_ELEMENTS 105
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#endif
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#define TWAQ_FREE 0
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#define TWAQ_BUSY 1
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#define TWAQ_PENDING 2
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#define TWAQ_COMPLETE 3
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#define TWAQ_IO_PENDING 4
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#define TWAQ_COUNT 5 /* total number of queues */
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#define TWA_DRIVER_VERSION_STRING "1.00.00.000"
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#define TWA_REQUEST_TIMEOUT_PERIOD 60 /* seconds */
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#define TWA_MESSAGE_SOURCE_CONTROLLER_ERROR 3
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/* Register offsets from base address. */
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#define TWA_CONTROL_REGISTER_OFFSET 0x0
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#define TWA_STATUS_REGISTER_OFFSET 0x4
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#define TWA_COMMAND_QUEUE_OFFSET 0x8
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#define TWA_RESPONSE_QUEUE_OFFSET 0xC
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#define TWA_COMMAND_QUEUE_OFFSET_LOW 0x20
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#define TWA_COMMAND_QUEUE_OFFSET_HIGH 0x24
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#define TWA_RESPONSE_QUEUE_LARGE_OFFSET 0x30
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#if defined(_KERNEL)
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#define TWA_WRITE_REGISTER(sc, offset, val) \
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bus_space_write_4(sc->twa_bus_iot, sc->twa_bus_ioh, offset, (uint32_t)val)
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#define TWA_WRITE_COMMAND_QUEUE(sc, val) \
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do { \
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if (TWA_64BIT_ADDRESSES) { \
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/* First write the low 4 bytes, then the high 4. */ \
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TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_LOW, \
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(uint32_t)(val)); \
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TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_HIGH,\
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(uint32_t)(((uint64_t)val)>>32)); \
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} else \
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TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET,\
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(uint32_t)(val)); \
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} while (0)
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#endif
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#define TWA_WRITE_COMMAND_QUEUE_HIGH(sc, val) \
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do { \
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TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_HIGH, \
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(uint32_t)(((uint64_t)val)>>32)); \
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} while (0)
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#define TWA_WRITE_COMMAND_QUEUE_LOW(sc, val) \
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do { \
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TWA_WRITE_REGISTER(sc, TWA_COMMAND_QUEUE_OFFSET_LOW, \
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(uint32_t)(val)); \
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} while (0)
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/* Control register bit definitions. */
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#define TWA_CONTROL_ISSUE_HOST_INTERRUPT 0x00000020
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#define TWA_CONTROL_DISABLE_INTERRUPTS 0x00000040
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#define TWA_CONTROL_ENABLE_INTERRUPTS 0x00000080
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#define TWA_CONTROL_ISSUE_SOFT_RESET 0x00000100
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#define TWA_CONTROL_CLEAR_ERROR_STATUS 0x00000200
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#define TWA_CONTROL_UNMASK_RESPONSE_INTERRUPT 0x00004000
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#define TWA_CONTROL_UNMASK_COMMAND_INTERRUPT 0x00008000
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#define TWA_CONTROL_MASK_RESPONSE_INTERRUPT 0x00010000
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#define TWA_CONTROL_MASK_COMMAND_INTERRUPT 0x00020000
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#define TWA_CONTROL_CLEAR_ATTENTION_INTERRUPT 0x00040000
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#define TWA_CONTROL_CLEAR_HOST_INTERRUPT 0x00080000
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#define TWA_CONTROL_CLEAR_PCI_ABORT 0x00100000
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#define TWA_CONTROL_CLEAR_QUEUE_ERROR 0x00400000
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#define TWA_CONTROL_CLEAR_PARITY_ERROR 0x00800000
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/* Status register bit definitions. */
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#define TWA_STATUS_ROM_BIOS_IN_SBUF 0x00000002
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#define TWA_STATUS_COMMAND_QUEUE_EMPTY 0x00001000
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#define TWA_STATUS_MICROCONTROLLER_READY 0x00002000
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#define TWA_STATUS_RESPONSE_QUEUE_EMPTY 0x00004000
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#define TWA_STATUS_COMMAND_QUEUE_FULL 0x00008000
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#define TWA_STATUS_RESPONSE_INTERRUPT 0x00010000
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#define TWA_STATUS_COMMAND_INTERRUPT 0x00020000
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#define TWA_STATUS_ATTENTION_INTERRUPT 0x00040000
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#define TWA_STATUS_HOST_INTERRUPT 0x00080000
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#define TWA_STATUS_PCI_ABORT_INTERRUPT 0x00100000
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#define TWA_STATUS_MICROCONTROLLER_ERROR 0x00200000
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#define TWA_STATUS_QUEUE_ERROR_INTERRUPT 0x00400000
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#define TWA_STATUS_PCI_PARITY_ERROR_INTERRUPT 0x00800000
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#define TWA_STATUS_MINOR_VERSION_MASK 0x0F000000
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#define TWA_STATUS_MAJOR_VERSION_MASK 0xF0000000
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#define TWA_STATUS_EXPECTED_BITS 0x00002000
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#define TWA_STATUS_UNEXPECTED_BITS 0x00F00000
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/* For use with the %b printf format. */
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#define TWA_STATUS_BITS_DESCRIPTION \
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"\20\15CMD_Q_EMPTY\16MC_RDY\17RESP_Q_EMPTY\20CMD_Q_FULL\21RESP_INTR\22CMD_INTR\23ATTN_INTR\24HOST_INTR\25PCI_ABRT\26MC_ERR\27Q_ERR\30PCI_PERR\n"
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/* Detect inconsistencies in the status register. */
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#define TWA_STATUS_ERRORS(x) \
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((x & TWA_STATUS_UNEXPECTED_BITS) && \
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(x & TWA_STATUS_MICROCONTROLLER_READY))
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/* PCI related defines. */
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#define TWA_IO_CONFIG_REG 0x10
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#define TWA_DEVICE_NAME "3ware 9000 series Storage Controller"
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#define TWA_VENDOR_ID 0x13C1
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#define TWA_DEVICE_ID_9K 0x1002
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#define TWA_PCI_CONFIG_CLEAR_PARITY_ERROR 0xc100
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#define TWA_PCI_CONFIG_CLEAR_PCI_ABORT 0x2000
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#define TWA_9550SX_DRAIN_COMPLETE 0xffff
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/* Command packet opcodes. */
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#define TWA_OP_NOP 0x00
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#define TWA_OP_INIT_CONNECTION 0x01
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#define TWA_OP_READ 0x02
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#define TWA_OP_WRITE 0x03
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#define TWA_OP_READVERIFY 0x04
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#define TWA_OP_VERIFY 0x05
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#define TWA_OP_ZEROUNIT 0x08
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#define TWA_OP_REPLACEUNIT 0x09
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#define TWA_OP_HOTSWAP 0x0A
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#define TWA_OP_SELFTESTS 0x0B
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#define TWA_OP_SYNC_PARAM 0x0C
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#define TWA_OP_REORDER_UNITS 0x0D
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#define TWA_OP_FLUSH 0x0E
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#define TWA_OP_EXECUTE_SCSI_COMMAND 0x10
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#define TWA_OP_ATA_PASSTHROUGH 0x11
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#define TWA_OP_GET_PARAM 0x12
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#define TWA_OP_SET_PARAM 0x13
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#define TWA_OP_CREATEUNIT 0x14
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#define TWA_OP_DELETEUNIT 0x15
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#define TWA_OP_DOWNLOAD_FIRMWARE 0x16
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#define TWA_OP_REBUILDUNIT 0x17
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#define TWA_OP_POWER_MANAGEMENT 0x18
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#define TWA_OP_REMOTE_PRINT 0x1B
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#define TWA_OP_RESET_FIRMWARE 0x1C
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#define TWA_OP_DEBUG 0x1D
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#define TWA_OP_DIAGNOSTICS 0x1F
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/* Misc defines. */
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#define TWA_ALIGNMENT 0x4
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#define TWA_MAX_UNITS 16
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#define TWA_9650_MAX_UNITS 32
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#define TWA_9690_MAX_UNITS 32
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#define TWA_INIT_MESSAGE_CREDITS 0x100
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#define TWA_SHUTDOWN_MESSAGE_CREDITS 0x001
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#define TWA_64BIT_SG_ADDRESSES 0x00000001
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#define TWA_EXTENDED_INIT_CONNECT 0x00000002
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#define TWA_BASE_MODE 1
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#define TWA_BASE_FW_SRL 24
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#define TWA_BASE_FW_BRANCH 0
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#define TWA_BASE_FW_BUILD 1
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#define TWA_CURRENT_FW_SRL 28
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#define TWA_CURRENT_FW_BRANCH 4
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#define TWA_CURRENT_FW_BUILD 9
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#define TWA_9000_ARCH_ID 0x5 /* 9000 series controllers */
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#define TWA_CTLR_FW_SAME_OR_NEWER 0x00000001
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#define TWA_CTLR_FW_COMPATIBLE 0x00000002
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#define TWA_BUNDLED_FW_SAFE_TO_FLASH 0x00000004
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#define TWA_CTLR_FW_RECOMMENDS_FLASH 0x00000008
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#define NUM_FW_IMAGE_CHUNKS 5
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#define TWA_MAX_IO_SIZE 0x20000 /* 128K */
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/* #define TWA_MAX_SG_ELEMENTS defined above */
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#define TWA_MAX_ATA_SG_ELEMENTS 60
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#define TWA_Q_LENGTH TWA_INIT_MESSAGE_CREDITS
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#define TWA_MAX_RESET_TRIES 3
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#define TWA_SECTOR_SIZE 0x200 /* generic I/O bufffer */
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#define TWA_SENSE_DATA_LENGTH 18
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#define TWA_MICROSECOND 1000000
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#define TWA_ERROR_LOGICAL_UNIT_NOT_SUPPORTED 0x010a
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#define TWA_ERROR_UNIT_OFFLINE 0x0128
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#define TWA_ERROR_MORE_DATA 0x0231
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/* Scatter/Gather list entry. */
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struct twa_sg {
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#if defined(_KERNEL)
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bus_addr_t address;
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#else
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uint32_t xx_address_xx; /* Fail if userland tries to use this */
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#endif
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uint32_t length;
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} __packed;
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/* 7000 structures. */
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struct twa_command_init_connect {
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uint8_t opcode:5; /* TWA_OP_INITCONNECTION */
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uint8_t res1:3;
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uint8_t size;
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uint8_t request_id;
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uint8_t res2;
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uint8_t status;
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uint8_t flags;
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uint16_t message_credits;
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uint32_t features;
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uint16_t fw_srl;
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uint16_t fw_arch_id;
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uint16_t fw_branch;
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uint16_t fw_build;
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uint32_t result;
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}__packed;
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struct twa_command_download_firmware {
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uint8_t opcode:5; /* TWA_DOWNLOAD_FIRMWARE */
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uint8_t sgl_offset:3;
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uint8_t size;
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uint8_t request_id;
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uint8_t unit;
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uint8_t status;
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uint8_t flags;
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uint16_t param;
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uint8_t sgl[1];
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} __packed;
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struct twa_command_reset_firmware {
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uint8_t opcode:5; /* TWA_OP_RESET_FIRMWARE */
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uint8_t res1:3;
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uint8_t size;
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uint8_t request_id;
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uint8_t unit;
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uint8_t status;
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uint8_t flags;
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uint8_t res2;
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uint8_t param;
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} __packed;
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struct twa_command_io {
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uint8_t opcode:5; /* TWA_OP_READ/TWA_OP_WRITE */
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uint8_t sgl_offset:3;
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uint8_t size;
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uint8_t request_id;
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uint8_t unit:4;
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uint8_t host_id:4;
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uint8_t status;
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uint8_t flags;
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uint16_t block_count;
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uint32_t lba;
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struct twa_sg sgl[TWA_MAX_SG_ELEMENTS];
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} __packed;
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struct twa_command_hotswap {
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uint8_t opcode:5; /* TWA_OP_HOTSWAP */
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uint8_t res1:3;
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uint8_t size;
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uint8_t request_id;
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uint8_t unit:4;
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uint8_t host_id:4;
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uint8_t status;
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uint8_t flags;
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uint8_t action;
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#define TWA_OP_HOTSWAP_REMOVE 0x00 /* remove assumed-degraded unit */
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#define TWA_OP_HOTSWAP_ADD_CBOD 0x01 /* add CBOD to empty port */
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#define TWA_OP_HOTSWAP_ADD_SPARE 0x02 /* add spare to empty port */
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uint8_t aport;
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} __packed;
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struct twa_command_param {
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uint8_t opcode:5; /* TWA_OP_GETPARAM, TWA_OP_SETPARAM */
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uint8_t sgl_offset:3;
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uint8_t size;
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uint8_t request_id;
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uint8_t unit:4;
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uint8_t host_id:4;
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uint8_t status;
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uint8_t flags;
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uint16_t param_count;
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uint8_t sgl[1];
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} __packed;
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struct twa_command_rebuildunit {
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uint8_t opcode:5; /* TWA_OP_REBUILDUNIT */
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uint8_t res1:3;
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uint8_t size;
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uint8_t request_id;
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uint8_t src_unit:4;
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uint8_t host_id:4;
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uint8_t status;
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uint8_t flags;
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uint8_t action:7;
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#define TWA_OP_REBUILDUNIT_NOP 0
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#define TWA_OP_REBUILDUNIT_STOP 2 /* stop all rebuilds */
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#define TWA_OP_REBUILDUNIT_START 4 /* start rebuild with lowest unit */
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#define TWA_OP_REBUILDUNIT_STARTUNIT 5 /* rebuild src_unit (not supported) */
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uint8_t cs:1; /* request state change on src_unit */
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uint8_t logical_subunit; /* for RAID10 rebuild of logical subunit */
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} __packed;
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struct twa_command_ata {
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uint8_t opcode:5; /* TWA_OP_ATA_PASSTHROUGH */
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uint8_t sgl_offset:3;
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uint8_t size;
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uint8_t request_id;
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uint8_t unit:4;
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uint8_t host_id:4;
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uint8_t status;
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uint8_t flags;
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uint16_t param;
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uint16_t features;
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uint16_t sector_count;
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uint16_t sector_num;
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uint16_t cylinder_lo;
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uint16_t cylinder_hi;
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uint8_t drive_head;
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uint8_t command;
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struct twa_sg sgl[TWA_MAX_ATA_SG_ELEMENTS];
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} __packed;
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struct twa_command_generic {
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uint8_t opcode:5;
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uint8_t sgl_offset:3;
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uint8_t size;
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uint8_t request_id;
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uint8_t unit:4;
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uint8_t host_id:4;
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uint8_t status;
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uint8_t flags;
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#define TWA_FLAGS_SUCCESS 0x00
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#define TWA_FLAGS_INFORMATIONAL 0x01
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#define TWA_FLAGS_WARNING 0x02
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#define TWA_FLAGS_FATAL 0x03
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#define TWA_FLAGS_PERCENTAGE (1<<8) /* bits 0-6 indicate completion percentage */
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uint16_t count; /* block count, parameter count, message credits */
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} __packed;
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/* Command packet header. */
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#pragma pack(1)
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struct twa_command_header {
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uint8_t sense_data[TWA_SENSE_DATA_LENGTH];
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struct {
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int8_t reserved[4];
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uint16_t error;
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uint8_t padding;
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struct {
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uint8_t severity:3;
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uint8_t reserved:5;
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} substatus_block;
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} status_block;
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uint8_t err_specific_desc[98];
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struct {
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uint8_t size_header;
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uint16_t reserved;
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uint8_t size_sense;
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} header_desc;
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} __packed;
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#pragma pack()
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/* Command packet - must be TWA_ALIGNMENT aligned. */
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union twa_command_7k {
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struct twa_command_init_connect init_connect;
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struct twa_command_download_firmware download_fw;
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struct twa_command_reset_firmware reset_fw;
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struct twa_command_param param;
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struct twa_command_generic generic;
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uint8_t padding[1024 - sizeof(struct twa_command_header)];
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} __packed;
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/* 9000 structures. */
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/* Command Packet. */
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struct twa_command_9k {
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struct {
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uint8_t opcode:5;
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uint8_t reserved:3;
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} command;
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uint8_t unit;
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uint16_t request_id;
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uint8_t status;
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uint8_t sgl_offset; /* offset (in bytes) to sg_list, from the end of sgl_entries */
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uint16_t sgl_entries;
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uint8_t cdb[16];
|
|
struct twa_sg sg_list[TWA_MAX_SG_ELEMENTS];
|
|
uint8_t padding[32];
|
|
} __packed;
|
|
|
|
|
|
|
|
/* Full command packet. */
|
|
struct twa_command_packet {
|
|
struct twa_command_header cmd_hdr;
|
|
union {
|
|
union twa_command_7k cmd_pkt_7k;
|
|
struct twa_command_9k cmd_pkt_9k;
|
|
} command;
|
|
} __packed;
|
|
|
|
|
|
/* Response queue entry. */
|
|
union twa_response_queue {
|
|
struct {
|
|
uint32_t undefined_1:4;
|
|
uint32_t response_id:8;
|
|
uint32_t undefined_2:20;
|
|
} u;
|
|
uint32_t value;
|
|
} __packed;
|
|
|
|
|
|
#define TWA_AEN_QUEUE_EMPTY 0x00
|
|
#define TWA_AEN_SOFT_RESET 0x01
|
|
#define TWA_AEN_SYNC_TIME_WITH_HOST 0x31
|
|
#define TWA_AEN_SEVERITY_ERROR 0x1
|
|
#define TWA_AEN_SEVERITY_WARNING 0x2
|
|
#define TWA_AEN_SEVERITY_INFO 0x3
|
|
#define TWA_AEN_SEVERITY_DEBUG 0x4
|
|
|
|
#define TWA_PARAM_DRIVESUMMARY 0x0002
|
|
#define TWA_PARAM_DRIVESTATUS 3
|
|
|
|
#define TWA_DRIVE_DETECTED 0x80
|
|
|
|
#define TWA_PARAM_DRIVE_TABLE 0x0200
|
|
#define TWA_PARAM_DRIVESIZEINDEX 2
|
|
#define TWA_PARAM_DRIVEMODELINDEX 3
|
|
|
|
#define TWA_PARAM_DRIVESIZE_LENGTH 4
|
|
#define TWA_PARAM_DRIVEMODEL_LENGTH 40
|
|
|
|
|
|
#define TWA_PARAM_VERSION 0x0402
|
|
#define TWA_PARAM_VERSION_Mon 2 /* monitor version [16] */
|
|
#define TWA_PARAM_VERSION_FW 3 /* firmware version [16] */
|
|
#define TWA_PARAM_VERSION_BIOS 4 /* BIOSs version [16] */
|
|
#define TWA_PARAM_VERSION_PCBA 5 /* PCB version [8] */
|
|
#define TWA_PARAM_VERSION_ATA 6 /* A-chip version [8] */
|
|
#define TWA_PARAM_VERSION_PCI 7 /* P-chip version [8] */
|
|
|
|
#define TWA_PARAM_CONTROLLER 0x0403
|
|
#define TWA_PARAM_CONTROLLER_PortCount 3 /* number of ports [1] */
|
|
|
|
#define TWA_PARAM_TIME_TABLE 0x40A
|
|
#define TWA_PARAM_TIME_SchedulerTime 0x3
|
|
|
|
#define TWA_9K_PARAM_DESCRIPTOR 0x8000
|
|
|
|
|
|
struct twa_param_9k {
|
|
uint16_t table_id;
|
|
uint8_t parameter_id;
|
|
uint8_t reserved;
|
|
uint16_t parameter_size_bytes;
|
|
uint16_t parameter_actual_size_bytes;
|
|
uint8_t data[1];
|
|
} __packed;
|
|
|
|
#endif /* !_PCI_TWAREG_H_ */
|