87 lines
3.2 KiB
C
87 lines
3.2 KiB
C
/* $NetBSD: pciide_cy693_reg.h,v 1.11 2009/10/19 18:41:15 bouyer Exp $ */
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/*
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* Copyright (c) 1998 Manuel Bouyer.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* Registers definitions for Contaq/Cypress's CY82693U PCI IDE controller.
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* Available from http://www.cypress.com/japan/prodgate/chip/cy82c693.html
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* This chip has 2 PCI IDE functions, each of them has only one channel
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* So there's no primary/secodary distinction in the registers defs.
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*/
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/* IDE control register */
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#define CY_CTRL 0x40
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#define CY_CTRL_RETRY 0x00002000
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#define CY_CTRL_SLAVE_PREFETCH 0x00000400
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#define CY_CTRL_POSTWRITE 0x00000200
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#define CY_CTRL_PREFETCH(drive) (0x00000100 << (2 * (drive)))
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#define CY_CTRL_POSTWRITE_LENGTH_MASK 0x00000030
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#define CY_CTRL_POSTWRITE_LENGTH_OFF 4
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#define CY_CTRL_PREFETCH_LENGTH_MASK 0x00000003
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#define CY_CTRL_PREFETCH_LENGTH_OFF 0
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/* IDE addr setup control register */
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#define CY_ADDR_CTRL 0x48
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#define CY_ADDR_CTRL_SETUP_OFF(drive) (4 * (drive))
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#define CY_ADDR_CTRL_SETUP_MASK(drive) \
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(0x00000007 << CY_ADDR_CTRL_SETUP_OFF(drive))
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/* command control register */
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#define CY_CMD_CTRL 0x4c
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#define CY_CMD_CTRL_IOW_PULSE_OFF(drive) (12 + 16 * (drive))
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#define CY_CMD_CTRL_IOW_REC_OFF(drive) (8 + 16 * (drive))
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#define CY_CMD_CTRL_IOR_PULSE_OFF(drive) (4 + 16 * (drive))
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#define CY_CMD_CTRL_IOR_REC_OFF(drive) (0 + 16 * (drive))
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static const int8_t cy_pio_pulse[] __unused =
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{9, 4, 3, 2, 2};
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static const int8_t cy_pio_rec[] __unused =
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{9, 7, 4, 2, 0};
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#ifdef unused
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static const int8_t cy_dma_pulse[] __unused =
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{7, 2, 2};
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static const int8_t cy_dma_rec[] __unused =
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{7, 1, 0};
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#endif
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/*
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* The cypress is quite weird: it uses 8-bit ISA registers to control
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* DMA modes.
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*/
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#define CY_DMA_ADDR 0x22
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#define CY_DMA_SIZE 0x2
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#define CY_DMA_IDX 0x00
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#define CY_DMA_IDX_PRIMARY 0x30
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#define CY_DMA_IDX_SECONDARY 0x31
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#define CY_DMA_IDX_TIMEOUT 0x32
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#define CY_DMA_DATA 0x01
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/* Multiword DMA transfer, for CY_DMA_IDX_PRIMARY or CY_DMA_IDX_SECONDARY */
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#define CY_DMA_DATA_MODE_MASK 0x03
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#define CY_DMA_DATA_SINGLE 0x04
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