253 lines
7.7 KiB
C
253 lines
7.7 KiB
C
/* $NetBSD: clock_pcctwo.c,v 1.17 2012/10/27 17:18:27 chs Exp $ */
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/*-
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* Copyright (c) 1999, 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Steve C. Woodford.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Glue for the Peripheral Channel Controller Two (PCCChip2) timers,
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* the Memory Controller ASIC (MCchip, and the Mostek clock chip found
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* on the MVME-1[67]7, MVME-1[67]2 and MVME-187 series of boards.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: clock_pcctwo.c,v 1.17 2012/10/27 17:18:27 chs Exp $");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/timetc.h>
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#include <machine/psl.h>
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#include <sys/bus.h>
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#include <dev/mvme/clockvar.h>
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#include <dev/mvme/pcctwovar.h>
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#include <dev/mvme/pcctworeg.h>
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int clock_pcctwo_match(device_t, cfdata_t, void *);
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void clock_pcctwo_attach(device_t, device_t, void *);
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struct clock_pcctwo_softc {
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struct clock_attach_args sc_clock_args;
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u_char sc_clock_lvl;
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struct timecounter sc_tc;
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};
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CFATTACH_DECL_NEW(clock_pcctwo, sizeof(struct clock_pcctwo_softc),
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clock_pcctwo_match, clock_pcctwo_attach, NULL, NULL);
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extern struct cfdriver clock_cd;
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static int clock_pcctwo_profintr(void *);
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static int clock_pcctwo_statintr(void *);
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static void clock_pcctwo_initclocks(void *, int, int);
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static u_int clock_pcctwo_getcount(struct timecounter *);
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static void clock_pcctwo_shutdown(void *);
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static struct clock_pcctwo_softc *clock_pcctwo_sc;
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static uint32_t clock_pcctwo_count;
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/* ARGSUSED */
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int
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clock_pcctwo_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct pcctwo_attach_args *pa = aux;
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/* Only one clock, please. */
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if (clock_pcctwo_sc)
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return (0);
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if (strcmp(pa->pa_name, clock_cd.cd_name))
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return (0);
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pa->pa_ipl = cf->pcctwocf_ipl;
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return (1);
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}
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/* ARGSUSED */
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void
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clock_pcctwo_attach(device_t parent, device_t self, void *aux)
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{
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struct clock_pcctwo_softc *sc;
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struct pcctwo_attach_args *pa;
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sc = clock_pcctwo_sc = device_private(self);
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pa = aux;
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if (pa->pa_ipl != CLOCK_LEVEL)
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panic("clock_pcctwo_attach: wrong interrupt level");
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sc->sc_clock_args.ca_arg = sc;
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sc->sc_clock_args.ca_initfunc = clock_pcctwo_initclocks;
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/* Do common portions of clock config. */
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clock_config(self, &sc->sc_clock_args, pcctwointr_evcnt(pa->pa_ipl));
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/* Ensure our interrupts get disabled at shutdown time. */
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(void) shutdownhook_establish(clock_pcctwo_shutdown, NULL);
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sc->sc_clock_lvl = (pa->pa_ipl & PCCTWO_ICR_LEVEL_MASK) |
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PCCTWO_ICR_ICLR | PCCTWO_ICR_IEN;
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/* Attach the interrupt handlers. */
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pcctwointr_establish(PCCTWOV_TIMER1, clock_pcctwo_profintr,
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pa->pa_ipl, NULL, &clock_profcnt);
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pcctwointr_establish(PCCTWOV_TIMER2, clock_pcctwo_statintr,
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pa->pa_ipl, NULL, &clock_statcnt);
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}
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void
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clock_pcctwo_initclocks(void *arg, int prof_us, int stat_us)
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{
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struct clock_pcctwo_softc *sc;
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sc = arg;
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER1_CONTROL, PCCTWO_TT_CTRL_COVF);
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pcc2_reg_write32(sys_pcctwo, PCC2REG_TIMER1_COUNTER, 0);
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pcc2_reg_write32(sys_pcctwo, PCC2REG_TIMER1_COMPARE,
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PCCTWO_US2LIM(prof_us));
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER1_CONTROL,
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PCCTWO_TT_CTRL_CEN | PCCTWO_TT_CTRL_COC | PCCTWO_TT_CTRL_COVF);
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER1_ICSR, sc->sc_clock_lvl);
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER2_CONTROL, PCCTWO_TT_CTRL_COVF);
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pcc2_reg_write32(sys_pcctwo, PCC2REG_TIMER2_COUNTER, 0);
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pcc2_reg_write32(sys_pcctwo, PCC2REG_TIMER2_COMPARE,
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PCCTWO_US2LIM(stat_us));
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER2_CONTROL,
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PCCTWO_TT_CTRL_CEN | PCCTWO_TT_CTRL_COC | PCCTWO_TT_CTRL_COVF);
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER2_ICSR, sc->sc_clock_lvl);
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sc->sc_tc.tc_get_timecount = clock_pcctwo_getcount;
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sc->sc_tc.tc_name = "pcctwo_count";
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sc->sc_tc.tc_frequency = PCCTWO_TIMERFREQ;
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sc->sc_tc.tc_quality = 100;
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sc->sc_tc.tc_counter_mask = ~0;
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tc_init(&sc->sc_tc);
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}
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/* ARGSUSED */
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u_int
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clock_pcctwo_getcount(struct timecounter *tc)
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{
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u_int cnt;
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uint32_t tc1, tc2;
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uint8_t cr;
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int s;
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s = splhigh();
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/*
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* There's no way to latch the counter and overflow registers
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* without pausing the clock, so compensate for the possible
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* race by checking for counter wrap-around and re-reading the
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* overflow counter if necessary.
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*
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* Note: This only works because we're at splhigh().
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*/
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tc1 = pcc2_reg_read32(sys_pcctwo, PCC2REG_TIMER1_COUNTER);
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cr = pcc2_reg_read(sys_pcctwo, PCC2REG_TIMER1_CONTROL);
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tc2 = pcc2_reg_read32(sys_pcctwo, PCC2REG_TIMER1_COUNTER);
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if (tc1 > tc2) {
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cr = pcc2_reg_read(sys_pcctwo, PCC2REG_TIMER1_CONTROL);
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tc1 = tc2;
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}
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cnt = clock_pcctwo_count;
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splx(s);
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/* XXX assume HZ == 100 */
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cnt += tc1 + (PCCTWO_TIMERFREQ / 100) * PCCTWO_TT_CTRL_OVF(cr);
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return cnt;
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}
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int
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clock_pcctwo_profintr(void *frame)
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{
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u_int8_t cr;
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u_int32_t tc;
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int s;
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s = splhigh();
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tc = pcc2_reg_read32(sys_pcctwo, PCC2REG_TIMER1_COUNTER);
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cr = pcc2_reg_read(sys_pcctwo, PCC2REG_TIMER1_CONTROL);
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if (tc > pcc2_reg_read32(sys_pcctwo, PCC2REG_TIMER1_COUNTER))
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cr = pcc2_reg_read(sys_pcctwo, PCC2REG_TIMER1_CONTROL);
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER1_CONTROL,
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PCCTWO_TT_CTRL_CEN | PCCTWO_TT_CTRL_COC | PCCTWO_TT_CTRL_COVF);
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER1_ICSR,
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clock_pcctwo_sc->sc_clock_lvl);
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splx(s);
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for (cr = PCCTWO_TT_CTRL_OVF(cr); cr; cr--) {
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/* XXX assume HZ == 100 */
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clock_pcctwo_count += PCCTWO_TIMERFREQ / 100;
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hardclock(frame);
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}
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return (1);
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}
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int
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clock_pcctwo_statintr(void *frame)
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{
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/* Disable the timer interrupt while we handle it. */
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER2_ICSR, 0);
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statclock((struct clockframe *) frame);
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER2_CONTROL, PCCTWO_TT_CTRL_COVF);
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pcc2_reg_write32(sys_pcctwo, PCC2REG_TIMER2_COUNTER, 0);
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pcc2_reg_write32(sys_pcctwo, PCC2REG_TIMER2_COMPARE,
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PCCTWO_US2LIM(CLOCK_NEWINT(clock_statvar, clock_statmin)));
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER2_CONTROL,
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PCCTWO_TT_CTRL_CEN | PCCTWO_TT_CTRL_COC | PCCTWO_TT_CTRL_COVF);
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER2_ICSR,
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clock_pcctwo_sc->sc_clock_lvl);
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return (1);
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}
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/* ARGSUSED */
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void
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clock_pcctwo_shutdown(void *arg)
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{
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/* Make sure the timer interrupts are turned off. */
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER1_CONTROL, PCCTWO_TT_CTRL_COVF);
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER1_ICSR, 0);
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER2_CONTROL, PCCTWO_TT_CTRL_COVF);
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pcc2_reg_write(sys_pcctwo, PCC2REG_TIMER2_ICSR, 0);
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}
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