344 lines
8.7 KiB
C
344 lines
8.7 KiB
C
/* $NetBSD: if_ath_cardbus.c,v 1.2 2004/05/08 23:40:01 christos Exp $ */
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/*
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* Copyright (c) 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* CardBus bus front-end for the AR5001 Wireless LAN 802.11a/b/g CardBus.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_ath_cardbus.c,v 1.2 2004/05/08 23:40:01 christos Exp $");
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#include "opt_inet.h"
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#include "opt_ns.h"
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#include "bpfilter.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/ioctl.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <machine/endian.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_ether.h>
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#include <net80211/ieee80211_compat.h>
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#include <net80211/ieee80211_var.h>
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#if NBPFILTER > 0
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#include <net/bpf.h>
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#endif
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/if_inarp.h>
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#endif
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#ifdef NS
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#include <netns/ns.h>
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#include <netns/ns_if.h>
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#endif
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/mii_bitbang.h>
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#include <dev/ic/athcompat.h>
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#include <dev/ic/athvar.h>
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#include <../contrib/sys/dev/ic/athhal.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/cardbus/cardbusvar.h>
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#include <dev/cardbus/cardbusdevs.h>
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/*
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* PCI configuration space registers
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*/
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#define ATH_PCI_MMBA 0x10 /* memory mapped base */
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struct ath_cardbus_softc {
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struct ath_softc sc_ath;
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/* CardBus-specific goo. */
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void *sc_ih; /* interrupt handle */
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cardbus_devfunc_t sc_ct; /* our CardBus devfuncs */
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cardbustag_t sc_tag; /* our CardBus tag */
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bus_size_t sc_mapsize; /* the size of mapped bus space region */
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pcireg_t sc_bar_val; /* value of the BAR */
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int sc_intrline; /* interrupt line */
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};
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int ath_cardbus_match(struct device *, struct cfdata *, void *);
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void ath_cardbus_attach(struct device *, struct device *, void *);
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int ath_cardbus_detach(struct device *, int);
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CFATTACH_DECL(ath_cardbus, sizeof(struct ath_cardbus_softc),
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ath_cardbus_match, ath_cardbus_attach, ath_cardbus_detach, ath_activate);
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void ath_cardbus_setup(struct ath_cardbus_softc *);
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int ath_cardbus_enable(struct ath_softc *);
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void ath_cardbus_disable(struct ath_softc *);
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void ath_cardbus_power(struct ath_softc *, int);
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int
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ath_cardbus_match(struct device *parent, struct cfdata *match,
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void *aux)
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{
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struct cardbus_attach_args *ca = aux;
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const char* devname;
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devname = ath_hal_probe(PCI_VENDOR(ca->ca_id),
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PCI_PRODUCT(ca->ca_id));
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if (devname)
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return (1);
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return (0);
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}
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void
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ath_cardbus_attach(struct device *parent, struct device *self,
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void *aux)
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{
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struct ath_cardbus_softc *csc = (void *)self;
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struct ath_softc *sc = &csc->sc_ath;
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struct cardbus_attach_args *ca = aux;
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cardbus_devfunc_t ct = ca->ca_ct;
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bus_addr_t adr;
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sc->sc_dmat = ca->ca_dmat;
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csc->sc_ct = ct;
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csc->sc_tag = ca->ca_tag;
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/*
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* Power management hooks.
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*/
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sc->sc_enable = ath_cardbus_enable;
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sc->sc_disable = ath_cardbus_disable;
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sc->sc_power = ath_cardbus_power;
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/*
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* Map the device.
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*/
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if (Cardbus_mapreg_map(ct, ATH_PCI_MMBA, CARDBUS_MAPREG_TYPE_MEM, 0,
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&sc->sc_st, &sc->sc_sh, &adr, &csc->sc_mapsize) == 0) {
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#if rbus
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#else
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(*ct->ct_cf->cardbus_mem_open)(cc, 0, adr, adr+csc->sc_mapsize);
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#endif
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csc->sc_bar_val = adr | CARDBUS_MAPREG_TYPE_MEM;
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}
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else {
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printf("%s: unable to map device registers\n",
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sc->sc_dev.dv_xname);
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return;
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}
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/*
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* Set up the PCI configuration registers.
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*/
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ath_cardbus_setup(csc);
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/* Remember which interrupt line. */
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csc->sc_intrline = ca->ca_intrline;
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/*
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* Finish off the attach.
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*/
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ath_attach(PCI_PRODUCT(ca->ca_id), sc);
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/*
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* Power down the socket.
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*/
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Cardbus_function_disable(csc->sc_ct);
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}
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int
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ath_cardbus_detach(struct device *self, int flags)
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{
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struct ath_cardbus_softc *csc = (void *)self;
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struct ath_softc *sc = &csc->sc_ath;
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struct cardbus_devfunc *ct = csc->sc_ct;
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int rv;
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#if defined(DIAGNOSTIC)
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if (ct == NULL)
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panic("%s: data structure lacks", sc->sc_dev.dv_xname);
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#endif
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rv = ath_detach(sc);
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if (rv)
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return (rv);
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/*
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* Unhook the interrupt handler.
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*/
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if (csc->sc_ih != NULL)
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cardbus_intr_disestablish(ct->ct_cc, ct->ct_cf, csc->sc_ih);
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csc->sc_ih = NULL;
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/*
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* Release bus space and close window.
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*/
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Cardbus_mapreg_unmap(ct, ATH_PCI_MMBA,
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sc->sc_st, sc->sc_sh, csc->sc_mapsize);
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return (0);
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}
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int
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ath_cardbus_enable(struct ath_softc *sc)
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{
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struct ath_cardbus_softc *csc = (void *) sc;
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cardbus_devfunc_t ct = csc->sc_ct;
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cardbus_chipset_tag_t cc = ct->ct_cc;
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cardbus_function_tag_t cf = ct->ct_cf;
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/*
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* Power on the socket.
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*/
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Cardbus_function_enable(ct);
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/*
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* Set up the PCI configuration registers.
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*/
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ath_cardbus_setup(csc);
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/*
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* Map and establish the interrupt.
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*/
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csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
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ath_intr, sc);
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if (csc->sc_ih == NULL) {
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printf("%s: unable to establish interrupt at %d\n",
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sc->sc_dev.dv_xname, csc->sc_intrline);
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Cardbus_function_disable(csc->sc_ct);
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return (1);
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}
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printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname,
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csc->sc_intrline);
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return (0);
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}
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void
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ath_cardbus_disable(struct ath_softc *sc)
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{
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struct ath_cardbus_softc *csc = (void *) sc;
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cardbus_devfunc_t ct = csc->sc_ct;
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cardbus_chipset_tag_t cc = ct->ct_cc;
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cardbus_function_tag_t cf = ct->ct_cf;
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/* Unhook the interrupt handler. */
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cardbus_intr_disestablish(cc, cf, csc->sc_ih);
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csc->sc_ih = NULL;
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/* Power down the socket. */
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Cardbus_function_disable(ct);
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}
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void
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ath_cardbus_power(struct ath_softc *sc, int why)
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{
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struct ath_cardbus_softc *csc = (void *) sc;
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printf("%s: ath_cardbus_power\n", sc->sc_dev.dv_xname);
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if (why == PWR_RESUME) {
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/*
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* Give the PCI configuration registers a kick
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* in the head.
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*/
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#ifdef DIAGNOSTIC
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if (ATH_IS_ENABLED(sc) == 0)
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panic("ath_cardbus_power");
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#endif
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ath_cardbus_setup(csc);
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}
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}
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void
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ath_cardbus_setup(struct ath_cardbus_softc *csc)
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{
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struct ath_softc *sc = &csc->sc_ath;
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cardbus_devfunc_t ct = csc->sc_ct;
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cardbus_chipset_tag_t cc = ct->ct_cc;
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cardbus_function_tag_t cf = ct->ct_cf;
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pcireg_t reg;
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(void)cardbus_setpowerstate(sc->sc_dev.dv_xname, ct, csc->sc_tag,
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PCI_PWR_D0);
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/* Make sure the right access type is on the CardBus bridge. */
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(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE);
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(*ct->ct_cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
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/* Program the BAR. */
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cardbus_conf_write(cc, cf, csc->sc_tag, ATH_PCI_MMBA,
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csc->sc_bar_val);
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/* Enable the appropriate bits in the PCI CSR. */
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reg = cardbus_conf_read(cc, cf, csc->sc_tag,
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CARDBUS_COMMAND_STATUS_REG);
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reg |= CARDBUS_COMMAND_MASTER_ENABLE | CARDBUS_COMMAND_MEM_ENABLE;
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cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_COMMAND_STATUS_REG,
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reg);
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/*
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* Make sure the latency timer is set to some reasonable
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* value.
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*/
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reg = cardbus_conf_read(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG);
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if (CARDBUS_LATTIMER(reg) < 0x20) {
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reg &= ~(CARDBUS_LATTIMER_MASK << CARDBUS_LATTIMER_SHIFT);
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reg |= (0x20 << CARDBUS_LATTIMER_SHIFT);
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cardbus_conf_write(cc, cf, csc->sc_tag, CARDBUS_BHLC_REG, reg);
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}
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}
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