530 lines
13 KiB
C
530 lines
13 KiB
C
/* $NetBSD: ioc.c,v 1.1 2000/05/09 21:56:01 bjh21 Exp $ */
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/*-
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* Copyright (c) 1998, 1999, 2000 Ben Harris
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* This file is part of NetBSD/arm26 -- a port of NetBSD to ARM2/3 machines. */
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/*
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* ioc.c - Acorn/ARM I/O Controller (Albion/VC2311/VL2311/VY86C410)
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*/
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#include <sys/param.h>
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__RCSID("$NetBSD: ioc.c,v 1.1 2000/05/09 21:56:01 bjh21 Exp $");
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/queue.h>
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#include <sys/systm.h>
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#include <machine/bus.h>
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#include <machine/irq.h>
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#include <machine/spl.h>
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#include <arch/arm26/arm26/cpuvar.h>
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#include <arch/arm26/iobus/iobusvar.h>
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#include <arch/arm26/iobus/iocvar.h>
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#include <arch/arm26/iobus/iocreg.h>
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#include "locators.h"
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static int ioc_match __P((struct device *parent, struct cfdata *cf, void *aux));
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static void ioc_attach __P((struct device *parent, struct device *self, void *aux));
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static int ioc_search __P((struct device *parent, struct cfdata *cf, void *aux));
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static int ioc_print __P((void *aux, const char *pnp));
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static int ioc_irq_clock __P((void *cookie));
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static int ioc_irq_statclock __P((void *cookie));
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struct ioc_softc {
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struct device sc_dev;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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struct irq_handler *sc_clkirq;
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struct irq_handler *sc_sclkirq;
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u_int8_t sc_ctl;
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};
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struct cfattach ioc_ca = {
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sizeof(struct ioc_softc), ioc_match, ioc_attach
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};
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extern struct cfdriver ioc_cd;
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/*
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* Autoconfiguration glue
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*/
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static int
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ioc_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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/*
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* This is tricky. Accessing non-existant devices in iobus
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* space can hang the machine (MEMC datasheet section 5.3.3),
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* so probes would have to be very delicate. This isn't
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* _much_ of a problem with the IOC, since all machines I know
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* of have exactly one.
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*/
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if (cf->cf_unit == 0)
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return 1;
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else
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return 0;
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}
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static void
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ioc_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct ioc_softc *sc = (void *)self;
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struct iobus_attach_args *ioa = aux;
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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sc->sc_bst = ioa->ioa_tag;
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if (bus_space_map(ioa->ioa_tag, ioa->ioa_base, 0x00200000,
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0, &(sc->sc_bsh)) != 0)
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panic("%s: couldn't map", sc->sc_dev.dv_xname);
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bst = sc->sc_bst;
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bsh = sc->sc_bsh;
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/* Now we need to set up bits of the IOC */
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/* Control register: All bits high (input) is probably safe */
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ioc_ctl_write(self, 0xff, 0xff);
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/*
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* IRQ/FIQ: mask out all, leave clearing latched interrupts
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* till someone asks.
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*
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* In fact, the masks will be in this state already. See
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* start.c for details.
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*/
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bus_space_write_1(bst, bsh, IOC_IRQMSKA, 0x00);
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bus_space_write_1(bst, bsh, IOC_IRQMSKB, 0x00);
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bus_space_write_1(bst, bsh, IOC_FIQMSK, 0x00);
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/*-
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* Timers:
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* Timers 0/1 are set up by ioc_initclocks (called by cpu_initclocks).
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* XXX What if we need timers before then?
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* Timer 2 is set up by whatever's connected to BAUD.
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* Timer 3 is set up by the arckbd driver.
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*/
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printf("\n");
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config_search(ioc_search, self, NULL);
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}
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extern struct bus_space ioc_bs_tag;
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static int
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ioc_search(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct ioc_softc *sc = (void *)parent;
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struct ioc_attach_args ioc;
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bus_space_tag_t bst = sc->sc_bst;
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bus_space_handle_t bsh = sc->sc_bsh;
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ioc.ioc_bank = cf->cf_loc[IOCCF_BANK];
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ioc.ioc_offset = cf->cf_loc[IOCCF_OFFSET];
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ioc.ioc_slow_t = bst;
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bus_space_subregion(bst, bsh, (ioc.ioc_bank << IOC_BANK_SHIFT)
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+ (IOC_TYPE_SLOW << IOC_TYPE_SHIFT)
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+ (ioc.ioc_offset >> 2),
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1 << IOC_BANK_SHIFT, &ioc.ioc_slow_h);
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ioc.ioc_medium_t = bst;
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bus_space_subregion(bst, bsh, (ioc.ioc_bank << IOC_BANK_SHIFT)
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+ (IOC_TYPE_MEDIUM << IOC_TYPE_SHIFT)
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+ (ioc.ioc_offset >> 2),
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1 << IOC_BANK_SHIFT, &ioc.ioc_medium_h);
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ioc.ioc_fast_t = bst;
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bus_space_subregion(bst, bsh, (ioc.ioc_bank << IOC_BANK_SHIFT)
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+ (IOC_TYPE_FAST << IOC_TYPE_SHIFT)
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+ (ioc.ioc_offset >> 2),
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1 << IOC_BANK_SHIFT, &ioc.ioc_fast_h);
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ioc.ioc_sync_t = bst;
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bus_space_subregion(bst, bsh, (ioc.ioc_bank << IOC_BANK_SHIFT)
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+ (IOC_TYPE_SYNC << IOC_TYPE_SHIFT)
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+ (ioc.ioc_offset >> 2),
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1 << IOC_BANK_SHIFT, &ioc.ioc_sync_h);
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if ((cf->cf_attach->ca_match)(parent, cf, &ioc) > 0)
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config_attach(parent, cf, &ioc, ioc_print);
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return 0;
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}
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static int
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ioc_print(aux, pnp)
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void *aux;
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const char *pnp;
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{
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struct ioc_attach_args *ioc = aux;
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if (ioc->ioc_bank != IOCCF_BANK_DEFAULT)
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printf(" bank %d", ioc->ioc_bank);
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if (ioc->ioc_offset != IOCCF_OFFSET_DEFAULT)
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printf(" offset 0x%02x", ioc->ioc_offset);
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return UNCONF;
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}
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/*
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* Control Register
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*/
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/*
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* ioc_ctl_{read,write}
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*
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* Functions to manipulate the IOC control register. The bottom six
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* bits of the control register map to bidirectional pins on the chip.
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* The output circuits are open-drain, so a pin is made an input by
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* writing '1' to it.
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*/
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u_int
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ioc_ctl_read(self)
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struct device *self;
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{
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struct ioc_softc *sc = (void *)self;
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return bus_space_read_1(sc->sc_bst, sc->sc_bsh, IOC_CTL);
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}
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void
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ioc_ctl_write(self, value, mask)
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struct device *self;
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u_int value, mask;
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{
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struct ioc_softc *sc = (void *)self;
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int s;
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bus_space_tag_t bst = sc->sc_bst;
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bus_space_handle_t bsh = sc->sc_bsh;
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s = splhigh();
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sc->sc_ctl = (sc->sc_ctl & ~mask) | (value & mask);
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bus_space_barrier(bst, bsh, IOC_CTL, 1, BUS_BARRIER_WRITE);
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bus_space_write_1(bst, bsh, IOC_CTL, sc->sc_ctl);
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bus_space_barrier(bst, bsh, IOC_CTL, 1, BUS_BARRIER_WRITE);
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splx(s);
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}
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/*
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* Interrupt handling
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*/
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struct irq_handler *
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ioc_irq_establish(self, irq, level, handler, cookie)
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struct device *self;
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int irq, level;
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int handler __P((void *));
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void *cookie;
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{
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/* struct ioc_softc *sc = (void *)self; */
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return irq_establish(irq, level, handler, cookie);
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}
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/*
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* Find out if an interrupt line is currently active
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*/
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int
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ioc_irq_status(self, irq)
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struct device *self;
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int irq;
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{
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struct ioc_softc *sc = (void *)self;
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bus_space_tag_t bst = sc->sc_bst;
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bus_space_handle_t bsh = sc->sc_bsh;
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if (irq < 8)
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return (bus_space_read_1(bst, bsh, IOC_IRQSTA) &
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IOC_IRQA_BIT(irq)) != 0;
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else
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return (bus_space_read_1(bst, bsh, IOC_IRQSTB) &
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IOC_IRQB_BIT(irq)) != 0;
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}
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u_int32_t
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ioc_irq_status_full(self)
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struct device *self;
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{
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struct ioc_softc *sc = (void *)self;
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bus_space_tag_t bst = sc->sc_bst;
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bus_space_handle_t bsh = sc->sc_bsh;
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#if 0 /* XXX */
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printf("IRQ mask: 0x%x\n",
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bus_space_read_1(bst, bsh, IOC_IRQMSKA) |
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(bus_space_read_1(bst, bsh, IOC_IRQMSKB) << 8));
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#endif
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return bus_space_read_1(bst, bsh, IOC_IRQSTA) |
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(bus_space_read_1(bst, bsh, IOC_IRQSTB) << 8);
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}
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void
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ioc_irq_setmask(self, mask)
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struct device *self;
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u_int32_t mask;
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{
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struct ioc_softc *sc = (void *)self;
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bus_space_tag_t bst = sc->sc_bst;
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bus_space_handle_t bsh = sc->sc_bsh;
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bus_space_write_1(bst, bsh, IOC_IRQMSKA, mask & 0xff);
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bus_space_write_1(bst, bsh, IOC_IRQMSKB, (mask >> 8) & 0xff);
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}
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void
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ioc_irq_waitfor(self, irq)
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struct device *self;
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int irq;
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{
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while (!ioc_irq_status(self, irq));
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}
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void
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ioc_irq_clear(self, mask)
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struct device *self;
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int mask;
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{
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struct ioc_softc *sc = (void *)self;
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bus_space_tag_t bst = sc->sc_bst;
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bus_space_handle_t bsh = sc->sc_bsh;
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bus_space_write_1(bst, bsh, IOC_IRQRQA, mask);
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}
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#if 0
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/*
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* ioc_get_irq_level:
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*
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* Find out the current level of an edge-triggered interrupt line.
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* Useful for the VIDC driver to know if it's in VSYNC if nothing
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* else.
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*/
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int ioc_get_irq_level(self, irq)
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struct device *self;
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int irq;
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{
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struct ioc_softc *sc = (void *)self;
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switch (irq) {
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case IOC_IRQ_IF:
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return (bus_space_read_1(sc->sc_bst, sc->sc_bsh, IOC_CTL) &
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IOC_CTL_NIF) != 0;
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case IOC_IRQ_IR:
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return (bus_space_read_1(sc->sc_bst, sc->sc_bsh, IOC_CTL) &
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IOC_CTL_IR) != 0;
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}
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panic("ioc_get_irq_level called for irq %d, which isn't edge-triggered",
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irq);
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}
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#endif /* 0 */
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/*
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* Counters
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*/
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void ioc_counter_start(self, counter, value)
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struct device *self;
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int counter, value;
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{
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struct ioc_softc *sc = (void *)self;
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bus_space_tag_t bst = sc->sc_bst;
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bus_space_handle_t bsh = sc->sc_bsh;
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int tlow, thigh, tgo;
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switch (counter) {
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case 0: tlow = IOC_T0LOW; thigh = IOC_T0HIGH; tgo = IOC_T0GO; break;
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case 1: tlow = IOC_T1LOW; thigh = IOC_T1HIGH; tgo = IOC_T1GO; break;
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case 2: tlow = IOC_T2LOW; thigh = IOC_T2HIGH; tgo = IOC_T2GO; break;
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case 3: tlow = IOC_T3LOW; thigh = IOC_T3HIGH; tgo = IOC_T3GO; break;
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default: panic("%s: ioc_counter_start: bad counter (%d)",
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self->dv_xname, counter);
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}
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bus_space_barrier(bst, bsh, tlow, tgo - tlow + 1, BUS_BARRIER_WRITE);
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bus_space_write_1(bst, bsh, tlow, value & 0xff);
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bus_space_write_1(bst, bsh, thigh, value >> 8 & 0xff);
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bus_space_barrier(bst, bsh, tlow, tgo - tlow + 1, BUS_BARRIER_WRITE);
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bus_space_write_1(bst, bsh, tgo, 0);
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bus_space_barrier(bst, bsh, tlow, tgo - tlow, BUS_BARRIER_WRITE);
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}
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/* Cache to save microtime recalculating it */
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static int t0_count;
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void
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cpu_initclocks()
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{
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struct device *self;
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struct ioc_softc *sc;
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#ifdef DIAGNOSTIC
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if (ioc_cd.cd_ndevs <= 0 || ioc_cd.cd_devs[0] == NULL)
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panic("cpu_initclocks: no ioc0");
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#endif
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self = ioc_cd.cd_devs[0];
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sc = (struct ioc_softc *)self;
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stathz = hz; /* XXX what _should_ it be? */
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if (hz == 0 || IOC_TIMER_RATE % hz != 0 ||
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(t0_count = IOC_TIMER_RATE / hz) > 65535)
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panic("ioc_initclocks: Impossible clock rate: %d Hz", hz);
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ioc_counter_start(self, 0, t0_count);
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sc->sc_clkirq = ioc_irq_establish(self, IOC_IRQ_TM0, IPL_CLOCK,
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ioc_irq_clock, NULL);
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printf("%s: %d Hz clock interrupting at %s\n",
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self->dv_xname, hz, irq_string(sc->sc_clkirq));
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irq_enable(sc->sc_clkirq);
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if (stathz) {
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setstatclockrate(stathz);
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sc->sc_sclkirq = ioc_irq_establish(self, IOC_IRQ_TM1,
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IPL_STATCLOCK,
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ioc_irq_statclock, NULL);
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printf("%s: %d Hz statclock interrupting at %s\n",
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self->dv_xname, stathz, irq_string(sc->sc_sclkirq));
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irq_enable(sc->sc_sclkirq);
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}
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}
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static int
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ioc_irq_clock(cookie)
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void *cookie;
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{
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hardclock(cookie);
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return IRQ_HANDLED;
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}
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static int
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ioc_irq_statclock(cookie)
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void *cookie;
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{
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statclock(cookie);
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return IRQ_HANDLED;
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}
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void
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setstatclockrate(hzrate)
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int hzrate;
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{
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struct device *self;
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int count;
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#ifdef DIAGNOSTIC
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if (ioc_cd.cd_ndevs <= 0 || ioc_cd.cd_devs[0] == NULL)
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panic("setstatclockrate: no ioc0");
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#endif
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self = ioc_cd.cd_devs[0];
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/* XXX This currently restarts the counter -- should it? */
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if (hzrate == 0 || IOC_TIMER_RATE % hzrate != 0 ||
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(count = IOC_TIMER_RATE / hz) > 65535)
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panic("Impossible statclock rate: %d Hz", hzrate);
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ioc_counter_start(self, 1, count);
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}
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void
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microtime(tv)
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struct timeval *tv;
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{
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struct device *self;
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struct ioc_softc *sc;
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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int t0, s, intbefore, intafter;
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#ifdef DIAGNOSTIC
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if (ioc_cd.cd_ndevs <= 0 || ioc_cd.cd_devs[0] == NULL)
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panic("microtime: no ioc0");
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#endif
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self = ioc_cd.cd_devs[0];
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sc = (struct ioc_softc *)self;
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bst = sc->sc_bst;
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bsh = sc->sc_bsh;
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s = splclock();
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*tv = time;
|
||
|
||
intbefore = ioc_irq_status(self, IOC_IRQ_TM0);
|
||
bus_space_write_1(bst, bsh, IOC_T0LATCH, 0);
|
||
t0 = bus_space_read_1(bst, bsh, IOC_T0LOW);
|
||
t0 += bus_space_read_1(bst, bsh, IOC_T0HIGH) << 8;
|
||
intafter = ioc_irq_status(self, IOC_IRQ_TM0);
|
||
|
||
splx(s);
|
||
|
||
/*
|
||
* If there's a timer interrupt pending, the counter has
|
||
* probably wrapped around once since "time" was last updated.
|
||
* Things are complicated by the fact that this could happen
|
||
* while we're trying to work out the time. We include some
|
||
* heuristics to spot this.
|
||
*/
|
||
|
||
if (intbefore || (intafter && t0 < t0_count / 2))
|
||
t0 -= t0_count;
|
||
|
||
tv->tv_usec += (t0_count - t0) / (IOC_TIMER_RATE / 1000000);
|
||
|
||
while (tv->tv_usec > 1000000) {
|
||
tv->tv_sec += 1;
|
||
tv->tv_usec -= 1000000;
|
||
}
|
||
}
|
||
|
||
void
|
||
delay(u_int usecs)
|
||
{
|
||
|
||
if (usecs <= 10 || cold)
|
||
cpu_delayloop(usecs * cpu_delay_factor);
|
||
else {
|
||
struct timeval start, gap, now, end;
|
||
|
||
microtime(&start);
|
||
gap.tv_sec = usecs / 1000000;
|
||
gap.tv_usec = usecs % 1000000;
|
||
timeradd(&start, &gap, &end);
|
||
do {
|
||
microtime(&now);
|
||
} while (timercmp(&now, &end, <));
|
||
}
|
||
|
||
}
|