190 lines
7.0 KiB
C
190 lines
7.0 KiB
C
/* $NetBSD: zsvar.h,v 1.1.1.1 1998/06/20 04:58:51 eeh Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)zsvar.h 8.1 (Berkeley) 6/11/93
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*/
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/*
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* Register layout is machine-dependent...
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*/
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struct zschan {
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volatile u_char zc_csr; /* ctrl,status, and indirect access */
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u_char zc_xxx0;
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volatile u_char zc_data; /* data */
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u_char zc_xxx1;
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};
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struct zsdevice {
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struct zschan zs_chan[2];
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};
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/*
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* Software state, per zs channel.
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*
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* The zs chip has insufficient buffering, so we provide a software
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* buffer using a two-level interrupt scheme. The hardware (high priority)
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* interrupt simply grabs the `cause' of the interrupt and stuffs it into
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* a ring buffer. It then schedules a software interrupt; the latter
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* empties the ring as fast as it can, hoping to avoid overflow.
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*
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* Interrupts can happen because of:
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* - received data;
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* - transmit pseudo-DMA done; and
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* - status change.
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* These are all stored together in the (single) ring. The size of the
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* ring is a power of two, to make % operations fast. Since we need two
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* bits to distinguish the interrupt type, and up to 16 for the received
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* data plus RR1 status, we use 32 bits per ring entry.
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*
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* When the value is a character + RR1 status, the character is in the
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* upper 8 bits of the RR1 status.
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*/
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/* 0 is reserved (means "no interrupt") */
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#define ZRING_RINT 1 /* receive data interrupt */
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#define ZRING_XINT 2 /* transmit done interrupt */
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#define ZRING_SINT 3 /* status change interrupt */
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#define ZRING_TYPE(x) ((x) & 3)
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#define ZRING_VALUE(x) ((x) >> 8)
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#define ZRING_MAKE(t, v) ((t) | (v) << 8)
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/* forard decl */
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struct zs_softc;
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struct zs_chanstate {
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struct zs_chanstate *cs_next; /* linked list for zshard() */
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struct zs_softc *cs_sc; /* pointer to softc */
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volatile struct zschan *cs_zc; /* points to hardware regs */
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int cs_unit; /* unit number */
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struct tty *cs_ttyp; /* ### */
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/*
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* We must keep a copy of the write registers as they are
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* mostly write-only and we sometimes need to set and clear
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* individual bits (e.g., in WR3). Not all of these are
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* needed but 16 bytes is cheap and this makes the addressing
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* simpler. Unfortunately, we can only write to some registers
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* when the chip is not actually transmitting, so whenever
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* we are expecting a `transmit done' interrupt the preg array
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* is allowed to `get ahead' of the current values. In a
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* few places we must change the current value of a register,
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* rather than (or in addition to) the pending value; for these
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* cs_creg[] contains the current value.
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*/
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u_char cs_creg[16]; /* current values */
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u_char cs_preg[16]; /* pending values */
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u_char cs_heldchange; /* change pending (creg != preg) */
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u_char cs_rr0; /* last rr0 processed */
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/* pure software data, per channel */
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char cs_softcar; /* software carrier */
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char cs_conk; /* is console keyboard, decode L1-A */
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char cs_brkabort; /* abort (as if via L1-A) on BREAK */
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char cs_kgdb; /* enter debugger on frame char */
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char cs_consio; /* port does /dev/console I/O */
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char cs_xxx; /* (spare) */
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int cs_speed; /* default baud rate (from ROM) */
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/*
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* The transmit byte count and address are used for pseudo-DMA
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* output in the hardware interrupt code. PDMA can be suspended
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* to get pending changes done; heldtbc is used for this. It can
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* also be stopped for ^S; this sets TS_TTSTOP in tp->t_state.
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*/
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int cs_tbc; /* transmit byte count */
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caddr_t cs_tba; /* transmit buffer address */
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int cs_heldtbc; /* held tbc while xmission stopped */
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/*
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* Printing an overrun error message often takes long enough to
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* cause another overrun, so we only print one per second.
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*/
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long cs_rotime; /* time of last ring overrun */
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long cs_fotime; /* time of last fifo overrun */
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/*
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* The ring buffer.
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*/
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u_int cs_rbget; /* ring buffer `get' index */
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volatile u_int cs_rbput; /* ring buffer `put' index */
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u_int cs_ringmask; /* mask, reflecting size of `rbuf' */
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int *cs_rbuf; /* type, value pairs */
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};
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/*
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* N.B.: the keyboard is channel 1, the mouse channel 0; ttyb is 1, ttya
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* is 0. In other words, the things are BACKWARDS.
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*/
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#define ZS_CHAN_A 1
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#define ZS_CHAN_B 0
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/*
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* Macros to read and write individual registers (except 0) in a channel.
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*
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* On the SparcStation the 1.6 microsecond recovery time is
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* handled in hardware. On the older Sun4 machine it isn't, and
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* software must deal with the problem.
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*
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* However, it *is* a problem on some Sun4m's (i.e. the SS20) (XXX: why?).
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* Thus we leave in the delay.
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*
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* XXX: (ABB) Think about this more.
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*/
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#if 0
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#define ZS_READ(c, r) zs_read(c, r)
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#define ZS_WRITE(c, r, v) zs_write(c, r, v)
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/*#define ZS_DELAY() (CPU_ISSUN4C ? (0) : delay(1))*/
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#define ZS_DELAY() (delay(1))
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#else /* SUN4 */
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#define ZS_READ(c, r) ((c)->zc_csr = (r), (c)->zc_csr)
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#define ZS_WRITE(c, r, v) ((c)->zc_csr = (r), (c)->zc_csr = (v))
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/* #define ZS_DELAY() (CPU_ISSUN4M ? delay(1) : 0) */
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#define ZS_DELAY() (0)
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#endif /* SUN4 */
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