386 lines
10 KiB
C
386 lines
10 KiB
C
/* $NetBSD: fpu.c,v 1.3 1996/03/14 19:41:49 christos Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)fpu.c 8.1 (Berkeley) 6/11/93
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*/
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#include <sys/param.h>
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#include <sys/proc.h>
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#include <sys/signal.h>
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#include <sys/systm.h>
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#include <sys/syslog.h>
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#include <sys/signalvar.h>
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#include <machine/instr.h>
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#include <machine/reg.h>
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#include <sparc/fpu/fpu_emu.h>
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#include <sparc/fpu/fpu_extern.h>
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/*
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* fpu_execute returns the following error numbers (0 = no error):
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*/
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#define FPE 1 /* take a floating point exception */
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#define NOTFPU 2 /* not an FPU instruction */
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/*
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* Translate current exceptions into `first' exception. The
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* bits go the wrong way for ffs() (0x10 is most important, etc).
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* There are only 5, so do it the obvious way.
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*/
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#define X1(x) x
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#define X2(x) x,x
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#define X4(x) x,x,x,x
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#define X8(x) X4(x),X4(x)
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#define X16(x) X8(x),X8(x)
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static char cx_to_trapx[] = {
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X1(FSR_NX),
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X2(FSR_DZ),
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X4(FSR_UF),
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X8(FSR_OF),
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X16(FSR_NV)
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};
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static u_char fpu_codes[] = {
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X1(FPE_FLTINEX_TRAP),
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X2(FPE_FLTDIV_TRAP),
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X4(FPE_FLTUND_TRAP),
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X8(FPE_FLTOVF_TRAP),
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X16(FPE_FLTOPERR_TRAP)
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};
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/*
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* The FPU gave us an exception. Clean up the mess. Note that the
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* fp queue can only have FPops in it, never load/store FP registers
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* nor FBfcc instructions. Experiments with `crashme' prove that
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* unknown FPops do enter the queue, however.
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*/
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void
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fpu_cleanup(p, fs)
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register struct proc *p;
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register struct fpstate *fs;
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{
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register int i, fsr = fs->fs_fsr, error;
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union instr instr;
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struct fpemu fe;
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switch ((fsr >> FSR_FTT_SHIFT) & FSR_FTT_MASK) {
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case FSR_TT_NONE:
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panic("fpu_cleanup 1"); /* ??? */
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break;
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case FSR_TT_IEEE:
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/* XXX missing trap address! */
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if ((i = fsr & FSR_CX) == 0)
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panic("fpu ieee trap, but no exception");
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trapsignal(p, SIGFPE, fpu_codes[i - 1]);
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break; /* XXX should return, but queue remains */
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case FSR_TT_UNFIN:
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case FSR_TT_UNIMP:
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if (fs->fs_qsize == 0)
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panic("fpu_cleanup 2");
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break;
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case FSR_TT_SEQ:
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panic("fpu sequence error");
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/* NOTREACHED */
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case FSR_TT_HWERR:
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log(LOG_ERR, "fpu hardware error (%s[%d])\n",
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p->p_comm, p->p_pid);
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uprintf("%s[%d]: fpu hardware error\n", p->p_comm, p->p_pid);
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trapsignal(p, SIGFPE, -1); /* ??? */
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goto out;
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default:
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printf("fsr=%x\n", fsr);
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panic("fpu error");
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}
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/* emulate the instructions left in the queue */
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fe.fe_fpstate = fs;
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for (i = 0; i < fs->fs_qsize; i++) {
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instr.i_int = fs->fs_queue[i].fq_instr;
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if (instr.i_any.i_op != IOP_reg ||
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(instr.i_op3.i_op3 != IOP3_FPop1 &&
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instr.i_op3.i_op3 != IOP3_FPop2))
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panic("bogus fpu queue");
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error = fpu_execute(&fe, instr);
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switch (error) {
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case 0:
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continue;
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case FPE:
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trapsignal(p, SIGFPE,
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fpu_codes[(fs->fs_fsr & FSR_CX) - 1]);
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break;
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case NOTFPU:
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trapsignal(p, SIGILL, 0); /* ??? code? */
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break;
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default:
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panic("fpu_cleanup 3");
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/* NOTREACHED */
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}
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/* XXX should stop here, but queue remains */
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}
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out:
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fs->fs_qsize = 0;
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}
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#ifdef notyet
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/*
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* If we have no FPU at all (are there any machines like this out
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* there!?) we have to emulate each instruction, and we need a pointer
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* to the trapframe so that we can step over them and do FBfcc's.
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* We know the `queue' is empty, though; we just want to emulate
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* the instruction at tf->tf_pc.
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*/
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fpu_emulate(p, tf, fs)
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struct proc *p;
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register struct trapframe *tf;
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register struct fpstate *fs;
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{
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do {
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fetch instr from pc
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decode
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if (integer instr) {
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/*
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* We do this here, rather than earlier, to avoid
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* losing even more badly than usual.
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*/
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if (p->p_addr->u_pcb.pcb_uw) {
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write_user_windows();
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if (rwindow_save(p))
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sigexit(p, SIGILL);
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}
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if (loadstore) {
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do_it;
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pc = npc, npc += 4
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} else if (fbfcc) {
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do_annul_stuff;
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} else
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return;
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} else if (fpu instr) {
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fe.fe_fsr = fs->fs_fsr &= ~FSR_CX;
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error = fpu_execute(&fe, fs, instr);
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switch (error) {
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etc;
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}
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} else
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return;
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if (want to reschedule)
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return;
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} while (error == 0);
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}
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#endif
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/*
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* Execute an FPU instruction (one that runs entirely in the FPU; not
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* FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be
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* modified to reflect the setting the hardware would have left.
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*
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* Note that we do not catch all illegal opcodes, so you can, for instance,
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* multiply two integers this way.
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*/
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int
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fpu_execute(fe, instr)
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register struct fpemu *fe;
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union instr instr;
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{
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register struct fpn *fp;
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register int opf, rs1, rs2, rd, type, mask, fsr, cx;
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register struct fpstate *fs;
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u_int space[4];
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/*
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* `Decode' and execute instruction. Start with no exceptions.
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* The type of any i_opf opcode is in the bottom two bits, so we
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* squish them out here.
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*/
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opf = instr.i_opf.i_opf;
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type = opf & 3;
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mask = "\0\0\1\3"[type];
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rs1 = instr.i_opf.i_rs1 & ~mask;
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rs2 = instr.i_opf.i_rs2 & ~mask;
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rd = instr.i_opf.i_rd & ~mask;
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#ifdef notdef
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if ((rs1 | rs2 | rd) & mask)
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return (BADREG);
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#endif
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fs = fe->fe_fpstate;
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fe->fe_fsr = fs->fs_fsr & ~FSR_CX;
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fe->fe_cx = 0;
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switch (opf >>= 2) {
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default:
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return (NOTFPU);
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case FMOV >> 2: /* these should all be pretty obvious */
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rs1 = fs->fs_regs[rs2];
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goto mov;
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case FNEG >> 2:
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rs1 = fs->fs_regs[rs2] ^ (1 << 31);
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goto mov;
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case FABS >> 2:
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rs1 = fs->fs_regs[rs2] & ~(1 << 31);
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mov:
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fs->fs_regs[rd] = rs1;
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fs->fs_fsr = fe->fe_fsr;
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return (0); /* success */
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case FSQRT >> 2:
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fpu_explode(fe, &fe->fe_f1, type, rs2);
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fp = fpu_sqrt(fe);
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break;
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case FADD >> 2:
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fpu_explode(fe, &fe->fe_f1, type, rs1);
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fpu_explode(fe, &fe->fe_f2, type, rs2);
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fp = fpu_add(fe);
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break;
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case FSUB >> 2:
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fpu_explode(fe, &fe->fe_f1, type, rs1);
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fpu_explode(fe, &fe->fe_f2, type, rs2);
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fp = fpu_sub(fe);
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break;
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case FMUL >> 2:
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fpu_explode(fe, &fe->fe_f1, type, rs1);
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fpu_explode(fe, &fe->fe_f2, type, rs2);
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fp = fpu_mul(fe);
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break;
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case FDIV >> 2:
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fpu_explode(fe, &fe->fe_f1, type, rs1);
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fpu_explode(fe, &fe->fe_f2, type, rs2);
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fp = fpu_div(fe);
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break;
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case FCMP >> 2:
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fpu_explode(fe, &fe->fe_f1, type, rs1);
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fpu_explode(fe, &fe->fe_f2, type, rs2);
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fpu_compare(fe, 0);
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goto cmpdone;
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case FCMPE >> 2:
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fpu_explode(fe, &fe->fe_f1, type, rs1);
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fpu_explode(fe, &fe->fe_f2, type, rs2);
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fpu_compare(fe, 1);
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cmpdone:
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/*
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* The only possible exception here is NV; catch it
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* early and get out, as there is no result register.
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*/
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cx = fe->fe_cx;
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fsr = fe->fe_fsr | (cx << FSR_CX_SHIFT);
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if (cx != 0) {
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if (fsr & (FSR_NV << FSR_TEM_SHIFT)) {
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fs->fs_fsr = (fsr & ~FSR_FTT) |
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(FSR_TT_IEEE << FSR_FTT_SHIFT);
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return (FPE);
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}
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fsr |= FSR_NV << FSR_AX_SHIFT;
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}
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fs->fs_fsr = fsr;
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return (0);
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case FSMULD >> 2:
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case FDMULX >> 2:
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if (type == FTYPE_EXT)
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return (NOTFPU);
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fpu_explode(fe, &fe->fe_f1, type, rs1);
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fpu_explode(fe, &fe->fe_f2, type, rs2);
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type++; /* single to double, or double to quad */
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fp = fpu_mul(fe);
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break;
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case FTOS >> 2:
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case FTOD >> 2:
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case FTOX >> 2:
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case FTOI >> 2:
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fpu_explode(fe, fp = &fe->fe_f1, type, rs2);
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type = opf & 3; /* sneaky; depends on instruction encoding */
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break;
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}
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/*
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* ALU operation is complete. Collapse the result and then check
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* for exceptions. If we got any, and they are enabled, do not
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* alter the destination register, just stop with an exception.
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* Otherwise set new current exceptions and accrue.
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*/
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fpu_implode(fe, fp, type, space);
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cx = fe->fe_cx;
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fsr = fe->fe_fsr;
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if (cx != 0) {
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mask = (fsr >> FSR_TEM_SHIFT) & FSR_TEM_MASK;
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if (cx & mask) {
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/* not accrued??? */
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fs->fs_fsr = (fsr & ~FSR_FTT) |
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(FSR_TT_IEEE << FSR_FTT_SHIFT) |
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(cx_to_trapx[(cx & mask) - 1] << FSR_CX_SHIFT);
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return (FPE);
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}
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fsr |= (cx << FSR_CX_SHIFT) | (cx << FSR_AX_SHIFT);
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}
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fs->fs_fsr = fsr;
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fs->fs_regs[rd] = space[0];
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if (type >= FTYPE_DBL) {
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fs->fs_regs[rd + 1] = space[1];
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if (type > FTYPE_DBL) {
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fs->fs_regs[rd + 2] = space[2];
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fs->fs_regs[rd + 3] = space[3];
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}
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}
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return (0); /* success */
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}
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