257 lines
7.2 KiB
C
257 lines
7.2 KiB
C
/* $NetBSD: a9wdt.c,v 1.4 2015/03/04 23:18:21 jmcneill Exp $ */
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: a9wdt.c,v 1.4 2015/03/04 23:18:21 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/device.h>
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#include <sys/wdog.h>
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#include <prop/proplib.h>
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#include <dev/sysmon/sysmonvar.h>
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#include <arm/cortex/a9tmr_reg.h>
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#include <arm/cortex/mpcore_var.h>
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static int a9wdt_match(device_t, cfdata_t, void *);
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static void a9wdt_attach(device_t, device_t, void *);
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struct a9wdt_softc {
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struct sysmon_wdog sc_smw;
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device_t sc_dev;
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bus_space_tag_t sc_memt;
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bus_space_handle_t sc_wdog_memh;
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u_int sc_wdog_max_period;
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u_int sc_wdog_period;
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u_int sc_wdog_prescaler;
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uint32_t sc_freq;
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uint32_t sc_wdog_load;
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uint32_t sc_wdog_ctl;
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bool sc_wdog_armed;
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};
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#ifndef A9WDT_PERIOD_DEFAULT
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#define A9WDT_PERIOD_DEFAULT 12
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#endif
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CFATTACH_DECL_NEW(a9wdt, sizeof(struct a9wdt_softc),
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a9wdt_match, a9wdt_attach, NULL, NULL);
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static bool attached;
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static inline uint32_t
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a9wdt_wdog_read(struct a9wdt_softc *sc, bus_size_t o)
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{
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return bus_space_read_4(sc->sc_memt, sc->sc_wdog_memh, o);
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}
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static inline void
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a9wdt_wdog_write(struct a9wdt_softc *sc, bus_size_t o, uint32_t v)
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{
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bus_space_write_4(sc->sc_memt, sc->sc_wdog_memh, o, v);
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}
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/* ARGSUSED */
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static int
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a9wdt_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct mpcore_attach_args * const mpcaa = aux;
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if (attached)
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return 0;
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if (!CPU_ID_CORTEX_A9_P(curcpu()->ci_arm_cpuid) &&
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!CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid))
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return 0;
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if (strcmp(mpcaa->mpcaa_name, cf->cf_name) != 0)
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return 0;
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/*
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* This isn't present on UP A9s (since CBAR isn't present).
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*/
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uint32_t mpidr = armreg_mpidr_read();
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if (mpidr == 0 || (mpidr & MPIDR_U))
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return 0;
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return 1;
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}
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static int
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a9wdt_tickle(struct sysmon_wdog *smw)
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{
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struct a9wdt_softc * const sc = smw->smw_cookie;
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/*
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* Cause the WDOG to restart counting.
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*/
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a9wdt_wdog_write(sc, TMR_LOAD, sc->sc_wdog_load);
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aprint_debug_dev(sc->sc_dev, "tickle\n");
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return 0;
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}
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static int
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a9wdt_setmode(struct sysmon_wdog *smw)
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{
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struct a9wdt_softc * const sc = smw->smw_cookie;
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if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
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/*
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* Emit magic sequence to turn off WDOG
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*/
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a9wdt_wdog_write(sc, TMR_WDOGDIS, TMR_WDOG_DISABLE_MAGIC1);
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a9wdt_wdog_write(sc, TMR_WDOGDIS, TMR_WDOG_DISABLE_MAGIC2);
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delay(1);
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sc->sc_wdog_ctl = a9wdt_wdog_read(sc, TMR_CTL);
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KASSERT((sc->sc_wdog_ctl & TMR_CTL_WDOG_MODE) == 0);
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aprint_debug_dev(sc->sc_dev, "setmode disable\n");
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return 0;
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}
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/*
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* If no changes, just tickle it and return.
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*/
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if (sc->sc_wdog_armed && smw->smw_period == sc->sc_wdog_period) {
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sc->sc_wdog_load = sc->sc_freq * sc->sc_wdog_period - 1;
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sc->sc_wdog_ctl = TMR_CTL_ENABLE | TMR_CTL_WDOG_MODE
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| __SHIFTIN(sc->sc_wdog_prescaler - 1, TMR_CTL_PRESCALER);
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a9wdt_wdog_write(sc, TMR_LOAD, sc->sc_wdog_load);
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a9wdt_wdog_write(sc, TMR_CTL, sc->sc_wdog_ctl);
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aprint_debug_dev(sc->sc_dev, "setmode refresh\n");
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return 0;
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}
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if (smw->smw_period == WDOG_PERIOD_DEFAULT) {
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sc->sc_wdog_period = A9WDT_PERIOD_DEFAULT;
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smw->smw_period = A9WDT_PERIOD_DEFAULT;
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}
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/*
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* Make sure we don't overflow the counter.
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*/
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if (smw->smw_period >= sc->sc_wdog_max_period) {
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return EINVAL;
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}
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sc->sc_wdog_load = sc->sc_freq * sc->sc_wdog_period - 1;
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sc->sc_wdog_ctl = TMR_CTL_ENABLE | TMR_CTL_WDOG_MODE
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| __SHIFTIN(sc->sc_wdog_prescaler - 1, TMR_CTL_PRESCALER);
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a9wdt_wdog_write(sc, TMR_LOAD, sc->sc_wdog_load);
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a9wdt_wdog_write(sc, TMR_CTL, sc->sc_wdog_ctl);
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aprint_debug_dev(sc->sc_dev, "setmode enable\n");
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return 0;
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}
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static void
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a9wdt_attach(device_t parent, device_t self, void *aux)
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{
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struct a9wdt_softc * const sc = device_private(self);
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struct mpcore_attach_args * const mpcaa = aux;
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prop_dictionary_t dict = device_properties(self);
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const char *cpu_type;
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sc->sc_dev = self;
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sc->sc_memt = mpcaa->mpcaa_memt;
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bus_space_subregion(sc->sc_memt, mpcaa->mpcaa_memh,
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TMR_WDOG_BASE, TMR_WDOG_SIZE, &sc->sc_wdog_memh);
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/*
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* This runs at the ARM PERIPHCLOCK which should be 1/2 of the
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* CPU clock. The MD code should have setup our frequency for us.
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*/
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prop_dictionary_get_uint32(dict, "frequency", &sc->sc_freq);
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sc->sc_wdog_ctl = a9wdt_wdog_read(sc, TMR_CTL);
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sc->sc_wdog_armed = (sc->sc_wdog_ctl & TMR_CTL_WDOG_MODE) != 0;
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if (sc->sc_wdog_armed) {
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sc->sc_wdog_prescaler =
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__SHIFTOUT(sc->sc_wdog_ctl, TMR_CTL_PRESCALER) + 1;
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sc->sc_freq /= sc->sc_wdog_prescaler;
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sc->sc_wdog_load = a9wdt_wdog_read(sc, TMR_LOAD);
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sc->sc_wdog_period = (sc->sc_wdog_load + 1) / sc->sc_freq;
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} else {
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sc->sc_wdog_period = A9WDT_PERIOD_DEFAULT;
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sc->sc_wdog_prescaler = 1;
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/*
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* Let's hope the timer frequency isn't prime.
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*/
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for (size_t div = 256; div >= 2; div++) {
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if (sc->sc_freq % div == 0) {
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sc->sc_wdog_prescaler = div;
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break;
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}
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}
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sc->sc_freq /= sc->sc_wdog_prescaler;
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}
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sc->sc_wdog_max_period = UINT32_MAX / sc->sc_freq;
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/*
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* Does the config file tell us to turn on the watchdog?
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*/
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if (device_cfdata(self)->cf_flags & 1)
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sc->sc_wdog_armed = true;
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aprint_naive("\n");
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if (CPU_ID_CORTEX_A5_P(curcpu()->ci_arm_cpuid)) {
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cpu_type = "A5";
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} else {
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cpu_type = "A9";
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}
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aprint_normal(": %s Watchdog Timer, default period is %u seconds%s\n",
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cpu_type, sc->sc_wdog_period,
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sc->sc_wdog_armed ? " (armed)" : "");
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sc->sc_smw.smw_name = device_xname(self);
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sc->sc_smw.smw_cookie = sc;
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sc->sc_smw.smw_setmode = a9wdt_setmode;
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sc->sc_smw.smw_tickle = a9wdt_tickle;
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sc->sc_smw.smw_period = sc->sc_wdog_period;
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if (sc->sc_wdog_armed) {
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int error = sysmon_wdog_setmode(&sc->sc_smw, WDOG_MODE_KTICKLE,
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sc->sc_wdog_period);
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if (error)
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aprint_error_dev(self,
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"failed to start kernel tickler: %d\n", error);
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}
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}
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